VHDL-边沿触发的加法计数器与七段数码管显示

  将加法计数器的输出DOUT作为七段数码管的输入，显示计数的结果。

该程序由四部分组成，分别是：加法计数器、数码管显示、通用偶数分频器、顶层调用文件。

1）顶层调用文件

--数码管显示

--通过拨码开关控制CLK,EN,LOAD；
--通过独立按键控制RST.

--v1.0 使用拨码开关产生时钟信号，不稳定。
--v1.1 增加分频器，以此产生时钟信号

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity led_sm is	
	port
	(	
	    inCLK,RST_in,EN_in,LOAD_in: IN STD_LOGIC;
		data_hex7:out std_logic_vector(7 downto 0);--数码管段码输出
		com:out std_logic_vector(3 downto 0)--位码输出		
	);
end led_sm;

architecture Lin of led_sm is
	
	component DECL7S is
	port
	(
		data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		LED7S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		com : out std_logic_vector(3 downto 0) -- 选通引脚
	);
	end component DECL7S;

	component CNT10 is	
	PORT 
	(
		CLK,RST,EN,LOAD:IN STD_LOGIC;  --
		DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);  --the data which was designed by me
		DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		COUT :OUT STD_LOGIC
	);
	end component CNT10;
	
	--design the signal of the data
	signal dd :STD_LOGIC_VECTOR(3 DOWNTO 0);
	signal num:STD_LOGIC_VECTOR(3 DOWNTO 0); 
	signal jinwei:STD_LOGIC;
	signal data_num:std_logic_vector(3 downto 0);
	
	--Converted data
	signal data_sm:std_logic_vector(7 downto 0);
	
begin
     dd <= "0000";

part1:  --CNT10 process
	CNT10 port map
	(
		CLK =>inCLK,RST =>RST_in, EN =>EN_in, LOAD =>LOAD_in, -- 
		DATA => dd,  --the first data is 0
		DOUT => num,
		COUT => jinwei
	);

	data_num <= num;

part2:  --the led-change process
	DECL7S port map
	(
		data_in => data_num,
		LED7S =>data_sm,
		com =>com
	);
	data_hex7<=data_sm;
END Lin;	

2）加法计数器

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

--v1.0 使用拨码开关产生时钟信号，不稳定。
--v1.1 增加分频器，以此产生时钟信号

ENTITY CNT10 IS
	PORT (CLK,RST,EN,LOAD:IN STD_LOGIC;  --
		DATA : IN STD_LOGIC_VECTOR(3 DOWNTO 0);  --the data which was designed by me
		DOUT : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		COUT :OUT STD_LOGIC);
	END CNT10;

ARCHITECTURE behav OF CNT10 IS
------------------------------
signal clk_tmp:std_logic;--半秒脉冲
--signal CLK:std_logic;-- time
--signal inCLK:std_logic;-- time

	component gen_div is--分频元件调用声明
	generic(div_param:integer:=10000000);--20000000分频的,产生半秒脉冲
	port
	(
		clk_in:in std_logic;
		bclk:out std_logic;
		resetb:in std_logic
	);
	end component gen_div;
	
	BEGIN 
     
gen_1s: --分频产生0.5s脉冲
		gen_div port map--分频元件例化
		(
			clk_in=>CLK,
			resetb=>not RST,
			bclk=>clk_tmp
		);
		 
		PROCESS (clk_tmp,RST,EN,LOAD)
		VARIABLE Q:STD_LOGIC_VECTOR(3 DOWNTO 0);
	BEGIN 
		IF RST='0' THEN Q:=(OTHERS=>'0'); 
		ELSIF RISING_EDGE(clk_tmp) THEN  --FALLING_EDGE(CLK)   CLK'EVENT AND   CLK ='0' 改为下降沿触发
		IF EN='1' THEN 
		IF(LOAD='0') THEN Q :=DATA; ELSE
			IF Q<9 THEN Q:=Q+1;
				ELSE Q := (OTHERS =>'0');
			END IF;
		END IF;
		END IF;
		END IF;
		
		IF Q="1001" THEN COUT<='1';
			ELSE COUT<='0'; END IF;
			DOUT <=Q;
		END PROCESS;

	END behav;

3）通用偶数分频器

--通用偶数分频器
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity  gen_div is
	generic(div_param:integer:=1);
	--分频因子,分频为2*div_param，默认2分频
	port
	(
		clk_in:in std_logic;--输入时钟
		bclk:out std_logic;--分频输出
		resetb:in std_logic--复位信号
	);
end gen_div;

architecture behave of gen_div is
signal tmp:std_logic;--输出暂存寄存器
signal cnt:integer range 0 to div_param:=0;--计数寄存器
begin
------------------------------
	process(clk_in,resetb)
	begin
		if resetb='1' then --reset有效时,bclk始终是0
			cnt<=0;
			tmp<='0';
		elsif rising_edge(clk_in) then
			cnt<=cnt+1;
			if cnt=div_param-1 then
				tmp<=not tmp;--取反信号
				cnt<=0;
			end if;
		end if;
	end process;
	bclk<=tmp;--输出
--------------------------------
end behave;

4）数码管显示

LIBRARY IEEE;
 USE IEEE.STD_LOGIC_1164.ALL;
 USE IEEE.STD_LOGIC_UNSIGNED.ALL;
 ENTITY DECL7S IS
	PORT (
		data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		LED7S : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		com : out std_logic_vector(3 downto 0) -- 选通引脚
		);
	END ;
ARCHITECTURE one OF DECL7S IS
BEGIN 
	com <= "1101"; --choose the shumaguan
	--引脚设置
	--com[3] PIN_141
	--com[2] PIN_142
	--com[1] PIN_144
	--com[0] PIN_6
	
	PROCESS (data_in) BEGIN 
		CASE data_in IS 
		WHEN "0000" => LED7S <= X"03";
		WHEN "0001" => LED7S <= X"9F";
		WHEN "0010" => LED7S <= X"25";
		WHEN "0011" => LED7S <= X"0d";
		WHEN "0100" => LED7S <= X"99";
		WHEN "0101" => LED7S <= X"49";
		WHEN "0110" => LED7S <= X"41";
		WHEN "0111" => LED7S <= X"1F";
		WHEN "1000" => LED7S <= X"01";
		WHEN "1001" => LED7S <= X"09";
	    when others=>LED7S<=X"FF";--支持0-9字符
		END CASE ;
	END PROCESS;
END one;

程序运行效果图