Uart接收状态机设计

使用一段式状态机，设计了一个uart接收器，采用16倍波特率采样，无奇偶校验。

状态转移表

仿真输出图，串口数据0x55

module uart_rx_fsm(clk_16,rx,data_out,ready);
    input clk_16,rx;
    output reg [7:0] data_out;
    output reg ready;
    
    reg[2:0] state;
    reg[3:0] count;
    reg[2:0] bits;
    reg[7:0] buffer;
    
    parameter IDLE = 0; //空闲状态
    parameter WAIT_S0 =1;//等待起始位中点
    parameter CHECK_S0 = 2;//复核起始位
    parameter WAIT_BIT = 3;//等待数据位中点
    parameter STORE_BIT = 4;//存储数据位
    parameter WAIT_STOP = 5;//等待停止位中点
    parameter CHECK_STOP = 6;//检查停止位是否正确
    
    always @(posedge clk_16)begin
        case(state)
            IDLE:begin count<=0;bits<=0;ready<=0;
                if (rx)     state<=IDLE;
                else        state <= WAIT_S0;
            end
            
            WAIT_S0:begin count <= count+1'd1;bits<=0;ready<=0;
                if(count == 6) state <= CHECK_S0;
                else                state <= WAIT_S0;
            end
            
            CHECK_S0:begin count<=0;bits<=0;ready<=0;
                if (rx)     state<=IDLE;
                else        state <= WAIT_BIT;
            end
            
            WAIT_BIT:begin count <= count+1'd1;ready<=0;
                if(count== 14) state <= STORE_BIT;
                else                state <= WAIT_BIT;
            end
            
            STORE_BIT:begin count <= 0;bits<=bits+1'd1;ready<=0; buffer[bits]<= rx;
                if(bits ==7) state <= WAIT_STOP;
                else state<=WAIT_BIT;               
            end
            
            WAIT_STOP:begin count <= count+1'd1;bits<=0;ready<=0;
                if(count == 14) state <= CHECK_STOP;
                else                state <= WAIT_STOP;
            end
            
            CHECK_STOP:begin count <= 0;bits<=0; state<=IDLE;               
                if(rx) begin data_out <= buffer;ready<=1; end
                else    ready<= 0;
            end
            default:state<=IDLE;
        endcase
    end 
endmodule