VHDL语法
case语句
case data is
when "000" => y <= "0000001";
when "001" => y <= "0000010";
when "010" => y <= "0000100";
when "011" => y <= "0001000";
when "100" => y <= "0010000";
when "101" => y <= "0100000";
when "110" => y <= "1000000";
when "111" => y <= "0000000";
end case;
LOOP语句
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity multiply4bit is
port(
a : in std_logic_vector (3 downto 0);
b : in std_logic_vector(3 downto 0);
result : out std_logic_vector(7 downto 0)
);
end entity;
architecture rtl of multiply4bit is
begin
process(a, b)
variable temp_m : std_logic_vector(4 downto 0);
variable sum : std_logic_vector(7 downto 0);
begin
sum := "00000000";
sum_loop :
for i in 0 to 3 loop
if( b(i) = '0') then
temp_m := "00000";
else
temp_m := '0' & a;
end if;
sum((4 + i) downto i) := sum((4 +i) downto 0) + temp_m;
end loop;
result <= sum;
end process;
end rtl;
1、FOR循环语句
[LOOP 标号：] FOR 循环变量 IN 循环次数范围 LOOP
顺序语句
END LOOP [LOOP 标号]；
A、循环变量i在信号、变量声明语句中不能出现，在使用时不必声明