verilog学习实例——编码器

16位编码器

module encoder_using_if(
binary_out,  //4位二进制编码输出
encoder_in   //16位输入
enable       //编码使能信号
);
//输出端口
output binary_out;
//输入端口
input enable
input[15:0] encoder_in;
//内部变量声明
reg[3:0]  binary_out;

always@(enable or encoder_in) begin                 //always语句产生组合逻辑，此句可改成always@(*)    
    if(enable) begin                                //使能信号enable必须为1，才可以译码
        if(encoder_in == 16'h0002) begin            // 输入的编码是0000_0000_0000_0010，译码为0001
            binary_out = 1;
        end if(encoder_in == 16'h0004) begin
            binary_out = 2;
        end if(encoder_in == 16'h0008) begin
            binary_out = 3;
        end if(encoder_in == 16'h0010) begin
            binary_out = 4;
        end if(encoder_in == 16'h0020) begin
            binary_out = 5;
        end if(encoder_in == 16'h0040) begin
            binary_out = 6;
        end if(encoder_in == 16'h0080) begin
            binary_out = 7;
        end if(encoder_in == 16'h0100) begin
            binary_out = 8;
        end if(encoder_in == 16'h0200) begin
            binary_out = 9;
        end if(encoder_in == 16'h0400) begin
            binary_out = 10;
        end if(encoder_in == 16'h0800) begin
            binary_out = 11;
        end if(encoder_in == 16'h1000) begin
            binary_out = 12;
        end if(encoder_in == 16'h2000) begin
            binary_out = 13;
        end if(encoder_in == 16'h4000) begin
            binary_out = 14;
        end if(encoder_in == 16'h8000) begin
            binary_out = 15;
        end 
    end
end
endmodule

• 综合的结果