在vivado编译时Generate Bitstream中运行不出来

在vivado编译时Generate Bitstream中运行不出来
警告：
[DRC UCIO-1] Unconstrained Logical Port: 1 out of 5 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_clk.
使用谷歌翻译之后是：
[DRC UCIO-1]无约束逻辑端口：5个逻辑端口中的1个没有为用户分配特定位置约束（LOC）。 这可能会导致I / O争用或与电路板电源或连接不兼容，从而影响性能，信号完整性或在极端情况下导致设备或其所连接的组件受损。 要更正此违规，请指定所有引脚位置。 除非所有逻辑端口都定义了用户指定的站点LOC约束，否则此设计将无法生成比特流。 要允许使用未指定的引脚位置创建比特流（不推荐），请使用以下命令：set_property SEVERITY {Warning} [get_drc_checks UCIO-1]。 注意：使用Vivado运行基础结构（例如，launch_runs Tcl命令）时，将此命令添加到.tcl文件，并将该文件添加为执行运行的write_bitstream步骤的预挂钩。 问题端口：sys_clk。
在xdc文档中插入：
set_property SEVERITY {Warning} [get_drc_checks UCIO-1]
即可运行