用硬件描述语言Verilog 设计一个抢答器

2. 设计一抢答器，要求如下：

抢答台数为6；具有抢答开始后20s倒计时，20秒倒计时后6人抢答显示超时，并报警；能显示超前抢答台号并显示犯规报警；系统复位后进入抢答状态，当有一路抢答按键按下，该路抢答信号将其余各路抢答信号封锁，同时铃声响起，直至该路按键松开，显示牌显示该路抢答台号。

module sponder1(clk,rset,start,spon1,spon2,spon3,spon4,spon5,spon6,qoutA,qoutB,who,cq_alarm,qd_alarm);
  input clk,rset,start;
  input spon1,spon2,spon3,spon4,spon5,spon6;
  output[3:0] qoutA,qoutB;
  output reg[2:0] who;
  output reg cq_alarm,qd_alarm;
  reg[4:0] qout;
  reg label,flag;
  reg i;
  reg[2:0] jishu;
  
  always @(posedge clk)
  begin
   if(!rset)
      begin
        qout<=19;
        who<=0;
        flag<=0;
        label<=0;
        i<=0;
        jishu<=0;
      end
    else 
    if(!flag&&i)
     begin
      if(qout==0)
       qout<=0;
        else
        qout<=qout-1;
     end  
 end

  assign qoutA=qout/10;
  assign qoutB=qout%10;
  
  always @(posedge clk)
  begin
    case(jishu)
      1: if(!spon1) begin if(i) label<=0; else label<=1; end
      2: if(!spon2) begin if(i) label<=0; else label<=1; end
      3: if(!spon3) begin if(i) label<=0; else label<=1; end
      4: if(!spon4) begin if(i) label<=0; else label<=1; end
      5: if(!spon5) begin if(i) label<=0; else label<=1; end
      6: if(!spon6) begin if(i) label<=0; else label<=1; end
     endcase
  end
  
  always @(posedge clk)
  begin
    if(spon1==1&&(!flag))
      begin
        who<=1;
        jishu<=1;
        label<=1;
        flag<=1;
      end
    end
    
    always @(posedge clk)
    begin
      if(spon2==1&&(!flag))
        begin
          who<=2;
          jishu<=2;
          label<=1;
          flag<=1;
        end
      end
      
      always @(posedge clk)
      begin
        if(spon3==1&&(!flag))
          begin
            who<=3;
            jishu<=3;
            label<=1;
            flag<=1;
          end
        end
        
    always @(posedge clk)
      begin
        if(spon4==1&&(!flag))
          begin
            who<=4;
            jishu<=4;
            label<=1;
            flag<=1;
          end
        end
        
    always @(posedge clk)
      begin
        if(spon5==1&&(!flag))
          begin
            who<=5;
            jishu<=5;
            label<=1;
            flag<=1;
          end
        end
        
    always @(posedge clk)
      begin
        if(spon6==1&&(!flag))
          begin
            who<=6;
            jishu<=6;
            label<=1;
            flag<=1;
          end
        end
        
     
     always @(posedge label)
      begin
        if(i)
          qd_alarm<=1;
      end
      
    always @(negedge label)
    begin
    qd_alarm<=0;
    cq_alarm<=0;
    end  
      
    always @(posedge clk)
    begin
      if(start) 
         i<=1;          
    end
    
   always @(posedge start)
   begin
   if(label)
     cq_alarm<=1;
   end
   
   always @(negedge start)
   begin
   if(cq_alarm)
     cq_alarm<=0;
   end
     
   
   
 endmodule

测试程序如下：

`timescale 1ns/1ns;
module sponder_tb;
  reg clk,rset,start;
  reg spon1,spon2,spon3,spon4,spon5,spon6;
  wire[2:0] who;
  wire[3:0] qoutA,qoutB;
  wire cq_alarm,qd_alarm;
  
  sponder1 u1(.clk(clk),.rset(rset),.start(start),.spon1(spon1),.spon2(spon2),
             .spon3(spon3),.spon4(spon4),.spon5(spon5),.spon6(spon6),.qoutA(qoutA),
             .qoutB(qoutB),.who(who),.cq_alarm(cq_alarm),.qd_alarm(qd_alarm));
  parameter DELY=100;
  always #(DELY/2) clk=~clk;
  initial
  begin
    clk=0;
    start=0;
    rset=0;
    #DELY rset=1;
    #(DELY*2) spon1=1;
    #DELY spon1=0;spon2=1;
    #DELY spon2=0;spon3=1;
    #DELY spon3=0;spon4=1;
    #DELY spon4=0;spon5=1;
    #DELY spon5=0;spon6=1;
    #DELY spon6=0;
    #DELY start=1;
    #DELY start=0;
    #(DELY*3) rset=0;
    #DELY rset=1;
    #DELY start=1;
    #DELY start=0;
    #(DELY*15) spon1=1;
    #DELY spon1=0;spon2=1;
    #(DELY*2) spon3=1;spon4=1;spon5=1;
    #DELY spon1=0;spon2=0;spon3=0;spon4=0;spon5=0;spon6=0;
    #(DELY*10) rset=0;
  end 
endmodule