VHDL设计一个同步置数、异步清零的D触发器

设计一个同步置数、异步清零的D触发器，其引脚名称和逻辑功能如下表所示。

LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY ddddd IS
PORT (clk, set, clr, d : IN STD_LOGIC;
q, nq : OUT STD_LOGIC);

END ddddd;
ARCHITECTURE ard OF ddddd IS
BEGIN
	PROCESS( clk,set,clr,d) is
	BEGIN
		IF clr='0' THEN
			q<='0';
			nq<='1';
		ELSE 
			IF (clk'EVENT AND clk='1') THEN
				IF  (SET='0' )THEN
					q<='1';
					nq<='0';
				ELSE
					IF d='1' THEN
						q<='1';
						nq<='0';
					ELSIF d='0' THEN
						q<='0';
						nq<='1';
					END IF;
				END IF;
			END IF;
		END IF;
	END PROCESS;
END ard;