ARMBoot-1.1.0 在 mini2440 开发板上的移植 之稻草人手记
ARMBoot-1.1.0 在 mini2440 开发板上的移植 之稻草人手记
< snallieATtomDOTcom >
作为U-boot的鼻祖-ARMboot以其小巧玲珑（代码压缩包仅有400K多），但又麻雀虽小，五脏俱全，不失为研究U-boot的第一步，
而且在ARMboot中处处还能看到U-boot的影子。好啦，开始我们的移植之旅吧。
移植目标： 驱动串口；驱动网络芯片dm9000；实现内核的下载（uImage）；实现启动 Linux kernel（zImage），实现Nand Flash启动
移植版本： ARMboot-1.1.0
ARMboot在哪： http://www.sourceforge.net/projects/armboot
交叉编译器： arm-linux-gcc 2.95.3 (在该版本下可以一次编译成功，所以采用该版本的交叉编译器)
开发板配置： RAM：64MB，Nor：2MB，Nand：64MB，Processor：Samsung S3C2440网卡芯片：dm9000
操作系统环境： RedHat Linux 9.0
环境查看：
编译器：
[root@arms root]# arm-linux-gcc -v
Reading specs from /usr/local/arm/2.95.3/lib/gcc-lib/arm-linux/2.95.3/specs
gcc version 2.95.3 20010315 (release)
源代码包：
[root@arms arms]# ls -l
total 428
-rw-r--r-- 1 root root 431099 Feb 25 2007 armboot-1.1.0.tgz
解压源码包：
[root@arms arms]# tar zxvf armboot-1.1.0.tgz
进入源码目录：（之后的所用工作均在该目录下完成）
[root@arms arms]# cd armboot-1.1.0
[root@arms armboot-1.1.0]#
armboot-1.1.0已经支持smdk2410开发板，该开发板和mini2440有一定的相似性，我们在
在SMDK2410开发板的基础上进行移植。
测试smdk2410是否能通过编译：
[root@arms armboot-1.1.0]# make distclean; make smdk2410_config ; make all
通过编译，查看生成的文件如下：
[root@arms armboot-1.1.0]# ls -altr
-rwxr-xr-x 1 root root 224812 May 24 08:43 armboot.srec
-rw-r--r-- 1 root root 28391 May 24 08:43 armboot.map
-rw-r--r-- 1 root root 210779 May 24 08:43 armboot.hex
-rwxr-xr-x 1 root root 74916 May 24 08:43 armboot.bin
-rwxr-xr-x 1 root root 91185 May 24 08:43 armboot
其中的armboot.bin即为最终的可以烧写到NandFlash的文件，由于代码还需修改，现在这个文件还不能适应mini2440的开发板环境，
上面的过程只是验证了smdk2410的配置即程序文件可以在arm-linux-gcc 2.95.3顺利编译通过，我们还需对代码做进一步的修改使得
其可以运行在到MINI2440上。
下面开始进行MINI2440的移植，为便于查看，将所涉及到的代码的行首都加了行号标示。
*************************************************************************************************************************************************
** 初步移植，复制关于SMDK2410的全部文件，并做相应地修改，在smdk2410的基础上构建MINI2440的代码环境
*************************************************************************************************************************************************
0） 清除上面的编译结果：
[root@arms armboot-1.1.0]# make distclean
1） 复制smdk2410_config的配置文件（注：所有板子的配置文件均在include/configs下）
[root@arms armboot-1.1.0]# cp include/configs/config_smdk2410.h include/configs/config_mini2440.h
复制完成后在config_mini2440.h做一个简单的修改标记-该变提示符：（建议：修改时先做做备份-即注释掉原来的代码，而后改成新的），
可用如下的sed 命令直接修改（用sed脚本修改只可执行1遍，切勿多次执行！）
[root@arms armboot-1.1.0]# sed -i'~' -e "/^/(#define/tCFG_PROMPT..*/)/ {N; s//(..*/)/n//////1 //// snallie, `date +%F_%H%M%S_%a`/n/1 //// snallie, `date +%F_%H%M%S_%a`/n/g; s/SMDK2410/ARMboot@MINI2440/2 }" include/configs/config_mini2440.h
或者用vi进行全屏幕编辑修改：
[root@arms armboot-1.1.0]# vi +99 include/configs/config_mini2440.h
具体修改的位置为：
改
99 #define CFG_PROMPT "SMDK2410 # " /* Monitor Command Prompt */
为：
99 //#define CFG_PROMPT "SMDK2410 # " /* Monitor Command Prompt */ // snallie, 2011-05-24_090111_Tue
100 #define CFG_PROMPT "ARMboot@MINI2440 # " /* Monitor Command Prompt */ // snallie, 2011-05-24_090111_Tue
2） 拷贝smdk2410的板级的程序文件为mini2440
[root@arms armboot-1.1.0]# cp -a board/smdk2410/ board/mini2440
3） 修改mini2440的板级的Makefile，文件位置在 board/mini2440/Makefile
改
28 OBJS := smdk2410.o flash.o env.o
为：
28 # OBJS := smdk2410.o flash.o env.o # snallie, 2011-05-24_091150_Tue
29 OBJS := mini2440.o flash.o env.o # snallie, 2011-05-24_091150_Tue
可用如下的sed 命令直接修改：（用sed脚本修改只可执行1遍，切勿多次执行！）
[root@arms armboot-1.1.0]# sed -i'~' -e "/^/(OBJS/t:= smdk2410.o..*/)/ {N; s//(..*/)/n/# /1 # snallie, `date +%F_%H%M%S_%a`/n/1 # snallie, `date +%F_%H%M%S_%a`/n/g; s/smdk2410/mini2440/2 }" board/mini2440/Makefile
或者用vi进行全屏幕编辑修改：
[root@arms armboot-1.1.0]# vi +28 board/mini2440/Makefile
4） 修改mini2440的板级的文件名，涉及文件为 board/mini2440/smdk2410.c
[root@arms armboot-1.1.0]# mv board/mini2440/smdk2410.c board/mini2440/mini2440.c
5） 修改顶层的Makefile：找到smdk2410_config，仿照smdk2410_config，添加mini2440_config,如下：
200 smdk2410_config : unconfig
201 @echo "Configuring for $(@:_config=) Board..." ; /
202 cd include ; /
203 echo "ARCH = arm" > config.mk ; /
204 echo "BOARD = smdk2410" >>config.mk ; /
205 echo "CPU = arm920t" >>config.mk ; /
206 echo "#include
207
208 # snallie, 2011-05-24_091758_Tue
209 mini2440_config : unconfig
210 @echo "Configuring for $(@:_config=) Board..." ; /
211 cd include ; /
212 echo "ARCH = arm" > config.mk ; /
213 echo "BOARD = mini2440" >>config.mk ; /
214 echo "CPU = arm920t" >>config.mk ; /
215 echo "#include
216
可用如下的sed 命令直接修改：（用sed脚本修改只可执行1遍，切勿多次执行！）
[root@arms armboot-1.1.0]# sed -i'~' -e "/smdk2410/,+7 {N;N;N;N;N;N;N; s//(..*/)/n/(..*/)/n/(..*/)/n/(..*/)/n/(..*/)/n/(..*/)/n/(..*/)/n/&/n# snallie, `date +%F_%H%M%S_%a`/n/1/n/2/n/3/n/4/n/5/n/6/n/7/n/g;s/smdk2410/mini2440/3;s/smdk2410/mini2440/3 } " -e "/backup/,/gtar/ {N;N;N; s//(..*/)/n/(..*/)/n/(..*/)/n/#/1/n#/2/n#/3/n/n# snallie, `date +%F_%H%M%S_%a`/n/1/n/2/n/3/n/g; s//"/([^/n]*/)/(/.tar/.gz/)//"+/$/$F-gk-%Y%m%d_%H%M%S/2/2 } " -e "/^armboot.bin/ {N;N;N; s//(..*/)/n/(..*/)/n/(..*/)/n//1/n/2/n# snallie, `date +%F_%H%M%S_%a`/n#/3/n/g }" Makefile
或者用vi进行全屏幕编辑修改：
[root@arms armboot-1.1.0]# vi +200 Makefile
注意：用vi手工修改时候，Makefile中的新添的210~215行的行首为制表符（TAB键），而不是空格，若输入的是空格，则编译出错
6） 程序的版本号有误，修改：include/version.h
改：
28 #define ARMBOOT_VERSION "ARMboot 1.0.2"
为：
28 //#define ARMBOOT_VERSION "ARMboot 1.0.2"
29 #define ARMBOOT_VERSION "ARMboot 1.1.0" // snallie, 2011-05-24_093229_Tue
可用如下的sed 命令直接修改：（用sed脚本修改只可执行1遍，切勿多次执行！）
[root@arms armboot-1.1.0]# sed -i'~' -e "/1.0.2/ {N; s//(..*/)/n//////1/n/1/g; s/1.0.2/"/1.1.0/"/t//// snallie, `date +%F_%H%M%S_%a`/n/2;}" include/version.h
或者用vi进行全屏幕编辑修改
[root@arms armboot-1.1.0]# vi +28 include/version.h
7） 关于SMDK2410的全部文件复制完成，编译测试：
[root@arms armboot-1.1.0]# make distclean; make mini2440_config; make all
通过编译！
*************************************************************************************************************************************************
** 进一步的移植，完成目标中的全部工作：驱动串口；驱动网络芯片dm9000；实现内核的下载（uImage）；实现启动 Linux kernel（zImage），实现Nand Flash启动
*************************************************************************************************************************************************
mini2440板配置初步完成，下面进行具体的移植工作，由于SMDK2410 的代码和MINI2440板子略有出入，SMDK2410代码认为程序是直接在NOR或RAM中运行，
而我们的代码最终是烧写到NandFlash中的，可NandFlash不具有片上执行代码的能力，所以程序启动的第一步就是要将整个的程序从NandFlash中搬移到RAM中，
即TEXT_BASE（配置在board/mini2440/config.mk文件中）的起始地址上去。另外SAMSUNG的S3C2440的处理器在系统启动时候会自动将NandFlash的前4K的代码
移动到内部的4K大小的称为Steppingstone的SRAM中运行，所以搬移用的代码必须放到程序映像的头部的4K的范围内，否则不能正常启动。综上所述，对SMDK2410
代码的改造主要为：实现代码的搬移工作，并将搬移用的代码放到程序映像的头部的4K的范围内；而后要驱动串口，这样我们才能获取到程序的运行时的输出状态
信息，串口驱动不起来等于是瞎子一样，所以串口驱动很重要，有了串口还可通过串口下载小体积的代码；在这之后再驱动网络芯片，实现网络下载代码，启动内核等等。
查看SMDK2410的代码，知道和CPU相关的代码通过在include/configs/config_smdk2410.h的宏定义CONFIG_S3C2410进行控制，和开发板SMDK2410相关的代码通过
在include/configs/config_smdk2410.h的宏定义CONFIG_SMDK2410进行控制，如下所示：
#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
#define CONFIG_SMDK2410 1 /* on an SAMSUNG SMDK2410 Board */
顺着这个线索，我们看看在原有的SMDK2410的代码有那些和CONFIG_S3C2410和CONFIG_SMDK2410的代码，以及它们分布在那些文件中：
和CONFIG_S3C2410相关的：
[root@arms armboot-1.1.0]# grep -rHn CONFIG_S3C2410 *
cpu/arm920t/interrupts.c:36:#elif defined(CONFIG_S3C2410)
cpu/arm920t/serial.c:25:#elif defined(CONFIG_S3C2410)
cpu/arm920t/start.S:134:#elif defined(CONFIG_S3C2410)
cpu/arm920t/start.S:153:#if defined(CONFIG_S3C2410)
include/configs/config_smdk2410.h:43:#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
和CONFIG_SMDK2410相关的：
[root@arms armboot-1.1.0]# grep -rHn CONFIG_SMDK2410 *
cpu/arm920t/serial.c:45:#elif defined(CONFIG_SMDK2410)
include/configs/config_smdk2410.h:44:#define CONFIG_SMDK2410 1 /* on an SAMSUNG SMDK2410 Board */
看程序的连接脚本： board/mini2440/armboot.lds
33 .text :
34 {
35 cpu/arm920t/start.o (.text)
36 *(.text)
37 }
知道程序的入口在cpu/arm920t/start.S上（现在U-boot中的该文件还保持着原有的风格）
查看该文件，知道整个程序的主要调用顺序为：
cpu_init_crit-> memsetup(在board/mini2440/memsetup.S中)
->start_armboot (在common/board.c中)
void start_armboot(void)进行了一系列的初始化工作，最后就进入
for (;;) {
main_loop(&bd);
}
主要是接受串口命令，分析并执行命令的循环中。
*************************************************************************************************************************************************
** 各个相关文件的修改 (为了便于说明，代码加了行号（所有新修改的代码均有snallie字样的注释，以示区别,并在代码段的下方对应中文注释说明)
*************************************************************************************************************************************************
////////////////////////
cpu/arm920t/start.S的修改
1 /*
2 * armboot - Startup Code for ARM920 CPU-core
3 *
4 * Copyright (c) 2001 Marius Gr鰃er
5 * Copyright (c) 2002 Alex Z黳ke
6 * Copyright (c) 2002 Gary Jennejohn
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27
28
29 #include "config.h"
30 #include "version.h"
31
32
33 /*
34 *************************************************************************
35 *
36 * Jump vector table as in table 3.1 in [1]
37 *
38 *************************************************************************
39 */
40
41
42 .globl _start
43 _start: b reset
44 ldr pc, _undefined_instruction
45 ldr pc, _software_interrupt
46 ldr pc, _prefetch_abort
47 ldr pc, _data_abort
48 ldr pc, _not_used
49 ldr pc, _irq
50 ldr pc, _fiq
51
52 _undefined_instruction: .word undefined_instruction
53 _software_interrupt: .word software_interrupt
54 _prefetch_abort: .word prefetch_abort
55 _data_abort: .word data_abort
56 _not_used: .word not_used
57 _irq: .word irq
58 _fiq: .word fiq
59
60 .balignl 16,0xdeadbeef
61
62
63 /*
64 *************************************************************************
65 *
66 * Startup Code (reset vector)
67 *
68 * do important init only if we don't start from memory!
69 * relocate armboot to ram
70 * setup stack
71 * jump to second stage
72 *
73 *************************************************************************
74 */
75
76 /*
77 * CFG_MEM_END is in the board dependent config-file (configs/config_BOARD.h)
78 */
79 _TEXT_BASE:
80 .word TEXT_BASE
81
82 .globl _armboot_start
83 _armboot_start:
84 .word _start
85
86 /*
87 * Note: armboot_end is defined by the (board-dependent) linker script
88 */
89 .globl _armboot_end
90 _armboot_end:
91 .word armboot_end
92
93 // start of snallie
94 .globl _bss_start
95 _bss_start:
96 .word __bss_start
97
98 .globl _bss_end
99 _bss_end:
100 .word armboot_end
101 // end of snallie
/*
* 94~100行 为新加入的代码，定义了2个全局变量，_bss_start和_bss_end，记录未初始化段的起止地址，其中的
* __bss_start和armboot_end 是在连接脚本 board/mini2440/armboot.lds 中定义的，后面309~317行用_bss_start
* 和_bss_end来进行未初始化段数据的初始清零工作。
*/
102
103 /*
104 * _armboot_real_end is the first usable RAM address behind armboot
105 * and the various stacks
106 */
107 .globl _armboot_real_end
108 _armboot_real_end:
109 .word 0x0badc0de
110
111 #ifdef CONFIG_USE_IRQ
112 /* IRQ stack memory (calculated at run-time) */
113 .globl IRQ_STACK_START
114 IRQ_STACK_START:
115 .word 0x0badc0de
116
117 /* IRQ stack memory (calculated at run-time) */
118 .globl FIQ_STACK_START
119 FIQ_STACK_START:
120 .word 0x0badc0de
121 #endif
122
123
124 /*
125 * the actual reset code
126 */
127
128 reset:
129 /*
130 * set the cpu to SVC32 mode
131 */
132 mrs r0,cpsr
133 bic r0,r0,#0x1f
134 orr r0,r0,#0xd3
135 msr cpsr,r0
136
137 /* turn off the watchdog */
138 #if defined(CONFIG_S3C2400)
139 #define pWTCON 0x15300000
140 /* Interupt-Controller base addresses */
141 #define INTMSK 0x14400008
142 /* clock divisor register */
143 #define CLKDIVN 0x14800014
144 #elif defined(CONFIG_S3C2410) || defined(CONFIG_S3C2440) // snallie
/* 144行 S3C2410和S3C2440的Watchdog以及中断屏蔽寄存器的地址相同，所以加入 || defined(CONFIG_S3C2440) 的判断 */
145 #define pWTCON 0x53000000
146 /* Interupt-Controller base addresses */
147 #define INTMSK 0x4A000008
148 #define INTSUBMSK 0x4A00001C
149 /* clock divisor register */
150 #define CLKDIVN 0x4C000014
151 #endif
152
153 // snallie
154 #define CLK_CTL_BASE 0x4C000000 /* tekkaman */
155 #define MDIV_405 0x7f << 12 /* tekkaman */
156 #define PSDIV_405 0x21 /* tekkaman */
157 #define MDIV_200 0xa1 << 12 /* tekkaman */
158 #define PSDIV_200 0x31 /* tekkaman */
159 // end of snallie
/* 154~158行引入tekkaman 的几个关于时钟除数因子的定义 */
160
161 ldr r0, =pWTCON
162 mov r1, #0x0
163 str r1, [r0]
164
165 /*
166 * mask all IRQs by setting all bits in the INTMR - default
167 */
168 mov r1, #0xffffffff
169 ldr r0, =INTMSK
170 str r1, [r0]
171 #if defined(CONFIG_S3C2410)
172 ldr r1, =0x3ff
173 ldr r0, =INTSUBMSK
174 str r1, [r0]
175 #endif
176
177 // start of snallie
178 #if defined(CONFIG_S3C2440)
179 ldr r1, =0x7ff
180 ldr r0, =INTSUBMSK
181 str r1, [r0]
182 #endif
183 // end of snallie
/*
* 178~183 为适应S3C2440中断屏蔽位寄存器的设置，事实上，S3C2440处理器复位后屏蔽全部的外部中断
* 168~183段的代码完全可以省略掉，为保持代码的完整行和历史风格，将其保留
*/
184
185 // start of snallie, SMDK2410 boot from NOR flash!
186 #if defined(CONFIG_S3C2410)
187 /* FCLK:HCLK:PCLK = 1:2:4 */
188 /* default FCLK is 120 MHz ! */
189 ldr r0, =CLKDIVN
190 mov r1, #3
191 str r1, [r0]
192
193 /*
194 * we do sys-critical inits only at reboot,
195 * not when booting from ram!
196 */
197 #ifdef CONFIG_INIT_CRITICAL
198 bl cpu_init_crit
199 #endif
200
201 relocate:
202 /*
203 * relocate armboot to RAM
204 */
205 adr r0, _start /* r0 <- current position of code */
206 ldr r2, _armboot_start
207 ldr r3, _armboot_end
208 sub r2, r3, r2 /* r2 <- size of armboot */
209 ldr r1, _TEXT_BASE /* r1 <- destination address */
210 add r2, r0, r2 /* r2 <- source end address */
211
212 /*
213 * r0 = source address
214 * r1 = target address
215 * r2 = source end address
216 */
217 copy_loop:
218 ldmia r0!, {r3-r10}
219 stmia r1!, {r3-r10}
220 cmp r0, r2
221 ble copy_loop
222
223 #if 0
224 /* try doing this stuff after the relocation */
225 ldr r0, =pWTCON
226 mov r1, #0x0
227 str r1, [r0]
228
229 /*
230 * mask all IRQs by setting all bits in the INTMR - default
231 */
232 mov r1, #0xffffffff
233 ldr r0, =INTMR
234 str r1, [r0]
235
236 /* FCLK:HCLK:PCLK = 1:2:4 */
237 /* default FCLK is 120 MHz ! */
238 ldr r0, =CLKDIVN
239 mov r1, #3
240 str r1, [r0]
241 /* END stuff after relocation */
242 #endif
243
244 /* set up the stack */
245 ldr r0, _armboot_end
246 add r0, r0, #CONFIG_STACKSIZE
247 sub sp, r0, #12 /* leave 3 words for abort-stack */
248
249 ldr pc, _start_armboot
250
251 _start_armboot: .word start_armboot
252 #endif
253 // end of snallie
/*
* 187~251 这段设置时钟和代码搬移即跳转的部分不适合MINI2440, 通过条件编译将其跳过：在 include/configs/config_mini2440.h
* 中我们将取消CONFIG_S3C2410的宏定义，取而代之的是定义CONFIG_S3C2440这个宏，所以187~251将在预处理时候被视为空
*/
/*
* 257~323部分为新修改的代码，以适应S3C2440 ，在 include/configs/config_mini2440.h 定义了CONFIG_S3C2440这个宏，
* 所以这段代码被编译
*/
254
255 // start of snallie, mini2440 boot from NAND flash
256 //#if defined(CONFIG_S3C2440) && defined(CONFIG_MINI2440)
257 #if defined(CONFIG_S3C2440)
258 /* FCLK:HCLK:PCLK = 1:4:8 */
259 ldr r0, =CLKDIVN
260 mov r1, #5
261 str r1, [r0]
262
263 mrc p15, 0, r1, c1, c0, 0
264 orr r1, r1, #0xc0000000
265 mcr p15, 0, r1, c1, c0, 0
266
267 mov r1, #CLK_CTL_BASE
268 mov r2, #MDIV_405 /* MPLL=405MHZ */
269 add r2, r2, #PSDIV_405
270 str r2, [r1, #0x04] /* MPLLCON tekkaman */
/*
* 259~270部分为设定工作时钟频率
*/
271
272 /*
273 * we do sys-critical inits only at reboot,
274 * not when booting from ram!
275 */
276 adr r0, _start /* r0 <- current position of code */ // snallie
277 ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ // snallie
278 cmp r0, r1 /* don't reloc during debug */ // snallie
279 blne cpu_init_crit // snallie
/* 判断代码的执行位置，以确定是否进行CPU的初始化：
* 276行为伪指令，工作是取_start这个标号的运行时的地址，277行取_TEXT_BASE单元中的一个字的数据
* 278行判断二者是否相等，若是不等则跳转到cpu_init_crit，进行CPU的初始化工作。
* 说明：这四条指令主要是为了是代码可以同时适应烧写到Flash运行和下载绝对地址TEXT_BASE处运行:
* (1)当烧写到Flash运行时候，这段代码的运行的起始地址为0x00000000,这时候_TEXT_BASE总是存储
* 常量TEXT_BASE（配置在board/mini2440/config.mk），比较后两者不等，表明是从Flash中启动的
* 所以要进行CPU等的初始化工作。
* （2）当代码是在下载绝对地址TEXT_BASE处运行时，_start的值和_TEXT_BASE中存放的值是相等的，
* 表明是在代码测试阶段时下载运行的，所以不必进行CPU等的初始化工作。
*/
280
281 /* set up the stack */ // snallie
282 ldr r0, _armboot_end // snallie
283 add r0, r0, #CONFIG_STACKSIZE // snallie
284 sub sp, r0, #12 /* leave 3 words for abort-stack */ // snallie
/*
* 在306行要调用C的函数
* int CopyCode2Ram(unsigned long start_addr, unsigned char *buf, int size)
* 进行代码的读出工作，所以282~284设定了一段堆栈，位于代码的下方（即程序代码部分的高地址部分），参见后面的
* 内存映像图。
*/
285
286 relocate:
287 /*
288 * relocate armboot to RAM
289 */
290 adr r0, _start /* r0 <- current position of code */
291 ldr r1, _TEXT_BASE /* r1 <- destination address */
292 cmp r0, r1 /* test if we run from flash or RAM */
293 beq call_start_armboot // snallie
/*
* 290~293行代码：在要搬移代码前，先判断代码是从Flash中开始运行的还是下载绝对地址TEXT_BASE处运行的，若是下载运行的，则
* 不必搬移，直接到call_start_armboot，否则进行代码的搬移。具体原因和对276行的注释相同。
*/
294 ldr r2, _armboot_start
295 ldr r3, _armboot_end
296 sub r2, r3, r2 /* r2 <- size of armboot */
/* 294~296行代码：求一下代码的长度，存放在r2寄存器中 */
297
298 /*
299 * r0 = source address
300 * r1 = target address
301 * r2 = size of armboot
302 */
303 // snallie, CopyCodeFromFlashToRam
304 // int CopyCode2Ram(unsigned long start_addr, unsigned char *buf, int size)
305 /*args:r0:source,r1:dest,r2:size*/
306 bl CopyCode2Ram //snallie, CopyCode2Ram.o must be linked within s3c24x0's steppingzone
/*
* 306行调用C的函数进行代码的搬移，ARM处理器下，汇编程序给C函数传递参数的方式为：参数个数小于4个时候，通过
* r0,r1,r2,r3,分别存放4个参数，若多于4个则其余的通过堆栈传递，这里CopyCode2Ram只有3个参数，分别放到
* r0,r1,r2中，r0存放代码在Flash上的开始地址，这里为0x00000000, r1存放代码搬移的起始地址TEXT_BASE（当前设定为0x31F00000），
* r2存放代码的大小
*/
307
308 call_start_armboot: // snallie
/*
* 准备跳转的start_armboot() 函数，309~317行将BSS段的全部数据清零，
* BSS存放的是未初始化的数据，包括外部的未初始化全局数据，函数内部的未初始化的静态变量等，均存放在BSS段中，
* 对于编译好的在操作系统下运行的C代码，这些段中的数据在C程序启动是会由编译器调用一段常规的启动例程进行清零的工作，
* 在这里我们的代码是独立运行的，不依赖于操作系统，我们要直接做这个工作。309~317 这段代码进行BSS段的全部数据清零工作。
* BSS段的数据在启动时清零的工作很重要（只可进行初始时候的一次清零处理！），不做清零处理，则程序运行时候会出现异常情况。
*/
309 clear_bss: // clear bss segment ,!! important !!, snallie
310 ldr r0, _bss_start /* find start of bss segment */
311 ldr r1, _bss_end /* stop here */
312 mov r2, #0x00000000 /* clear */
313
314 clbss_l:str r2, [r0] /* clear loop... */
315 add r0, r0, #4
316 cmp r0, r1
317 ble clbss_l // clear bss segment ,!! important !!, snallie
318
319 ldr pc, _start_armboot // snallie, call start_armboot(), and start.S ends here
/* 319行将跳转到start_armboot()函数，定义在 common/board.c中，此后start.S便完成其使命*/
320
321 _start_armboot: .word start_armboot
322
323 #endif
324 // end of snallie
325
326 /*
327 *************************************************************************
328 *
329 * CPU_init_critical registers
330 *
331 * setup important registers
332 * setup memory timing
333 *
334 *************************************************************************
335 */
336
337
338 cpu_init_crit:
339 /*
340 * flush v4 I/D caches
341 */
342 mov r0, #0
343 mcr p15, 0, r0, c7, c7, 0 // flush v3/v4 cache
344 mcr p15, 0, r0, c8, c7, 0 // flush v4 TLB
345
346 /*
347 * disable MMU stuff and caches
348 */
349 mrc p15, 0, r0, c1, c0, 0
350 bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
351 bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
352 orr r0, r0, #0x00000002 @ set bit 2 (A) Align
353 orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache // snallie
/* 353 加入设定指令Cache */
354 mcr p15, 0, r0, c1, c0, 0
355
356
357 /*
358 * before relocating, we have to setup RAM timing
359 * because memory timing is board-dependend, you will
360 * find a memsetup.S in your board directory.
361 */
362 mov ip, lr
363 bl memsetup
364 mov lr, ip
365
366 mov pc, lr
367
368
369
370
371 /*
372 *************************************************************************
373 *
374 * Interrupt handling
375 *
376 *************************************************************************
377 */
378
379 @
380 @ IRQ stack frame.
381 @
382 #define S_FRAME_SIZE 72
383
384 #define S_OLD_R0 68
385 #define S_PSR 64
386 #define S_PC 60
387 #define S_LR 56
388 #define S_SP 52
389
390 #define S_IP 48
391 #define S_FP 44
392 #define S_R10 40
393 #define S_R9 36
394 #define S_R8 32
395 #define S_R7 28
396 #define S_R6 24
397 #define S_R5 20
398 #define S_R4 16
399 #define S_R3 12
400 #define S_R2 8
401 #define S_R1 4
402 #define S_R0 0
403
404 #define MODE_SVC 0x13
405 #define I_BIT 0x80
406
407 /*
408 * use bad_save_user_regs for abort/prefetch/undef/swi ...
409 * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling
410 */
411
412 .macro bad_save_user_regs
413 sub sp, sp, #S_FRAME_SIZE
414 stmia sp, {r0 - r12} @ Calling r0-r12
415 add r8, sp, #S_PC
416
417 ldr r2, _armboot_end
418 add r2, r2, #CONFIG_STACKSIZE
419 sub r2, r2, #8
420 ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0
421 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC
422
423 add r5, sp, #S_SP
424 mov r1, lr
425 stmia r5, {r0 - r4} @ save sp_SVC, lr_SVC, pc, cpsr, old_r
426 mov r0, sp
427 .endm
428
429 .macro irq_save_user_regs
430 sub sp, sp, #S_FRAME_SIZE
431 stmia sp, {r0 - r12} @ Calling r0-r12
432 add r8, sp, #S_PC
433 stmdb r8, {sp, lr}^ @ Calling SP, LR
434 str lr, [r8, #0] @ Save calling PC
435 mrs r6, spsr
436 str r6, [r8, #4] @ Save CPSR
437 str r0, [r8, #8] @ Save OLD_R0
438 mov r0, sp
439 .endm
440
441 .macro irq_restore_user_regs
442 ldmia sp, {r0 - lr}^ @ Calling r0 - lr
443 mov r0, r0
444 ldr lr, [sp, #S_PC] @ Get PC
445 add sp, sp, #S_FRAME_SIZE
446 subs pc, lr, #4 @ return & move spsr_svc into cpsr
447 .endm
448
449 .macro get_bad_stack
450 ldr r13, _armboot_end @ setup our mode stack
451 add r13, r13, #CONFIG_STACKSIZE @ resides at top of normal stack
452 sub r13, r13, #8
453
454 str lr, [r13] @ save caller lr / spsr
455 mrs lr, spsr
456 str lr, [r13, #4]
457
458 mov r13, #MODE_SVC @ prepare SVC-Mode
459 @ msr spsr_c, r13
460 msr spsr, r13
461 mov lr, pc
462 movs pc, lr
463 .endm
464
465 .macro get_irq_stack @ setup IRQ stack
466 ldr sp, IRQ_STACK_START
467 .endm
468
469 .macro get_fiq_stack @ setup FIQ stack
470 ldr sp, FIQ_STACK_START
471 .endm
472
473 /*
474 * exception handlers
475 */
476 .align 5
477 undefined_instruction:
478 get_bad_stack
479 bad_save_user_regs
480 bl do_undefined_instruction
481
482 .align 5
483 software_interrupt:
484 get_bad_stack
485 bad_save_user_regs
486 bl do_software_interrupt
487
488 .align 5
489 prefetch_abort:
490 get_bad_stack
491 bad_save_user_regs
492 bl do_prefetch_abort
493
494 .align 5
495 data_abort:
496 get_bad_stack
497 bad_save_user_regs
498 bl do_data_abort
499
500 .align 5
501 not_used:
502 get_bad_stack
503 bad_save_user_regs
504 bl do_not_used
505
506 #ifdef CONFIG_USE_IRQ
507
508 .align 5
509 irq:
510 get_irq_stack
511 irq_save_user_regs
512 bl do_irq
513 irq_restore_user_regs
514
515 .align 5
516 fiq:
517 get_fiq_stack
518 /* someone ought to write a more effiction fiq_save_user_regs */
519 irq_save_user_regs
520 bl do_fiq
521 irq_restore_user_regs
522
523 #else
524
525 .align 5
526 irq:
527 get_bad_stack
528 bad_save_user_regs
529 bl do_irq
530
531 .align 5
532 fiq:
533 get_bad_stack
534 bad_save_user_regs
535 bl do_fiq
536
537 #endif
538
539 .align 5
540 .globl reset_cpu
541 reset_cpu:
542 mov ip, #0
543 mcr p15, 0, ip, c7, c7, 0 @ invalidate cache
544 mcr p15, 0, ip, c8, c7, 0 @ flush TLB (v4)
545 mrc p15, 0, ip, c1, c0, 0 @ get ctrl register
546 bic ip, ip, #0x000f @ ............wcam
547 bic ip, ip, #0x2100 @ ..v....s........
548 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
549 mov pc, r0
////////////////////////
board/mini2440/memsetup.S 的修改
1 /*
2 * Memory Setup stuff - taken from blob memsetup.S
3 *
4 * Copyright (C) 1999 2000 2001 Erik Mouw ([email protected]) and
5 * Jan-Derk Bakker ([email protected])
6 *
7 * Modified for the Samsung SMDK2410 by
8 * (C) Copyright 2002
9 * David Mueller, ELSOFT AG,
10 *
11 * See file CREDITS for list of people who contributed to this
12 * project.
13 *
14 * This program is free software; you can redistribute it and/or
15 * modify it under the terms of the GNU General Public License as
16 * published by the Free Software Foundation; either version 2 of
17 * the License, or (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful,
20 * but WITHOUT ANY WARRANTY; without even the implied warranty of
21 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
22 * GNU General Public License for more details.
23 *
24 * You should have received a copy of the GNU General Public License
25 * along with this program; if not, write to the Free Software
26 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
27 * MA 02111-1307 USA
28 */
29
30
31
32 #include "config.h"
33 #include "version.h"
34
35
36 /* some parameters for the board */
37
38 /*
39 *
40 * Taken from linux/arch/arm/boot/compressed/head-s3c2410.S
41 *
42 * Copyright (C) 2002 Samsung Electronics SW.LEE
43 *
44 */
45
46 #define BWSCON 0x48000000
47
48 /* BWSCON */
49 #define DW8 (0x0)
50 #define DW16 (0x1)
51 #define DW32 (0x2)
52 #define WAIT (0x1<<2)
53 #define UBLB (0x1<<3)
54
55 #define B1_BWSCON (DW32)
56 #define B2_BWSCON (DW16)
57 #define B3_BWSCON (DW16 + WAIT + UBLB)
58 #define B4_BWSCON (DW16)
59 #define B5_BWSCON (DW16)
60 #define B6_BWSCON (DW32)
61 #define B7_BWSCON (DW32)
62
63 /* BANK0CON */
64 #define B0_Tacs 0x0 /* 0clk */
65 #define B0_Tcos 0x0 /* 0clk */
66 #define B0_Tacc 0x7 /* 14clk */
67 #define B0_Tcoh 0x0 /* 0clk */
68 #define B0_Tah 0x0 /* 0clk */
69 #define B0_Tacp 0x0
70 #define B0_PMC 0x0 /* normal */
71
72 /* BANK1CON */
73 #define B1_Tacs 0x0 /* 0clk */
74 #define B1_Tcos 0x0 /* 0clk */
75 #define B1_Tacc 0x7 /* 14clk */
76 #define B1_Tcoh 0x0 /* 0clk */
77 #define B1_Tah 0x0 /* 0clk */
78 #define B1_Tacp 0x0
79 #define B1_PMC 0x0
80
81 #define B2_Tacs 0x0
82 #define B2_Tcos 0x0
83 #define B2_Tacc 0x7
84 #define B2_Tcoh 0x0
85 #define B2_Tah 0x0
86 #define B2_Tacp 0x0
87 #define B2_PMC 0x0
88
89 #define B3_Tacs 0x0 /* 0clk */
90 #define B3_Tcos 0x3 /* 4clk */
91 #define B3_Tacc 0x7 /* 14clk */
92 #define B3_Tcoh 0x1 /* 1clk */
93 #define B3_Tah 0x0 /* 0clk */
94 #define B3_Tacp 0x3 /* 6clk */
95 #define B3_PMC 0x0 /* normal */
96
97 #define B4_Tacs 0x0 /* 0clk */
98 #define B4_Tcos 0x0 /* 0clk */
99 #define B4_Tacc 0x7 /* 14clk */
100 #define B4_Tcoh 0x0 /* 0clk */
101 #define B4_Tah 0x0 /* 0clk */
102 #define B4_Tacp 0x0
103 #define B4_PMC 0x0 /* normal */
104
105 #define B5_Tacs 0x0 /* 0clk */
106 #define B5_Tcos 0x0 /* 0clk */
107 #define B5_Tacc 0x7 /* 14clk */
108 #define B5_Tcoh 0x0 /* 0clk */
109 #define B5_Tah 0x0 /* 0clk */
110 #define B5_Tacp 0x0
111 #define B5_PMC 0x0 /* normal */
112
113 #define B6_MT 0x3 /* SDRAM */
114 #define B6_Trcd 0x1
115 #define B6_SCAN 0x1 /* 9bit */
116
117 #define B7_MT 0x3 /* SDRAM */
118 #define B7_Trcd 0x1 /* 3clk */
119 #define B7_SCAN 0x1 /* 9bit */
120
121 /* REFRESH parameter */
122 #define REFEN 0x1 /* Refresh enable */
123 #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */
124 #define Trp 0x0 /* 2clk */
125 #define Trc 0x3 /* 7clk */
126 #define Tchr 0x2 /* 3clk */
127 #define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */
128 /**************************************/
129
130 _TEXT_BASE:
131 .word TEXT_BASE
132
133 .globl memsetup
134 memsetup:
135 /* memory control configuration */
136 /* make r0 relative the current location so that it */
137 /* reads SMRDATA out of FLASH rather than memory ! */
138 ldr r0, =SMRDATA
139 ldr r1, _TEXT_BASE
140 sub r0, r0, r1
141 ldr r1, =BWSCON /* Bus Width Status Controller */
142 add r2, r0, #13*4
143 0:
144 ldr r3, [r0], #4
145 str r3, [r1], #4
146 cmp r2, r0
147 bne 0b
148
149 /* everything is fine now */
150 mov pc, lr
151
152 .ltorg
153 /* the literal pools origin */
154 #if defined(CONFIG_SMDK2410) // snallie
155 SMRDATA:
156 .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
157 .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))
158 .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))
159 .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))
160 .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))
161 .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))
162 .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))
163 .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))
164 .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))
165 .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)
166 .word 0x32
167 .word 0x30
168 .word 0x30
169 #endif // snallie
/* 将 155~169行的内容通过条件编译取消掉 ，直接使用 172~203 行的部分，以适应MINI2440开发板 */
170
171 // start of snallie
172 #if defined(CONFIG_MINI2440)
173 SMRDATA:
174 .word 0x2211d110
175 .word 0x00000700
176 .word 0x00000700
177 .word 0x00000700
178 .word 0x0001c740
179 .word 0x00000700
180 .word 0x0001c740
181 .word 0x00018005
182 .word 0x00018005
183 .word 0x008e0459
184 .word 0x000000b2
185 .word 0x00000030
186 .word 0x00000030
187
188 // snallie, Sun Feb 6 10:09:44 HKT 2011
189 // .word 0x22111112
190 // .word 0x00000700
191 // .word 0x00000700
192 // .word 0x00000700
193 // .word 0x00000700
194 // .word 0x00000700
195 // .word 0x00000700
196 // .word 0x00018009
197 // .word 0x00018009
198 // .word 0x008e04eb
199 // .word 0x000000b2
200 // .word 0x00000030
201 // .word 0x00000030
202
203 #endif
204 // end of snallie
/* 170~204行为MINI2440开发板关于存储器控制的配置数据 */
//////////////////
board/mini2440/armboot.lds 的修改
1 /*
2 * (C) Copyright 2002
3 * Gary Jennejohn, DENX Software Engineering,
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
25 /*OUTPUT_FORMAT("elf32-arm", "elf32-arm", "elf32-arm")*/
26 OUTPUT_ARCH(arm)
27 ENTRY(_start)
28 SECTIONS
29 {
30 . = 0x00000000;
31
32 . = ALIGN(4);
33 .text :
34 {
35 cpu/arm920t/start.o (.text)
36 board/mini2440/memsetup.o (.text) /* snallie */
37 board/mini2440/boot_init.o (.text) /* snallie */
/*
* 36~37行控制将start.o，memsetup.o，boot_init.o 放在程序映像的前4K的部分，
* 不放在这里则程序的初始化部分将得不到运行，boot_init.o有boot_init.c编译而来，是新引入的文件，后面有说明
*/
38 *(.text)
39 }
40
41 . = ALIGN(4);
42 .rodata : { *(.rodata) }
43
44 . = ALIGN(4);
45 .data : { *(.data) }
46
47 . = ALIGN(4);
48 .got : { *(.got) }
49
50 . = ALIGN(4);
51 __bss_start = .; /* snallie */
/* 51行定义了一个新的符号地址，供cpu/arm920t/start.S 中的第95行使用，以便记录BSS段的起始地址 */
52 .bss : { *(.bss) }
53
54 armboot_end = .;
55 }
/////////////
新引入一个boot_init.c，在MINI2440的配套盘上的u-boot-1.1.6中可找到，
放到 board/mini2440 目录下，（随之还引入几个相关文件随后进行说明）并作少许改动如下：
1 //#include
2 //#include
3 #include
/*
* 第1行的common.h用不到，去掉，ARMboot-1.1.0中已经有了一个s3c2410.h，但是不适合boot_init.c 使用，
* 去掉，引入一个新的s3c2410a.h 供boot_init.c使用，该文件只改这些。主要是cpu/arm920t/start.S中调用了
* 这个文件中的int CopyCode2Ram(unsigned long start_addr, unsigned char *buf, int size)
*/
4
5 #define GSTATUS1 (*(volatile unsigned int *)0x560000B0)
6 #define BUSY 1
7
8 /* 供外部调用的函数 */
9 void nand_init_ll(void);
10 void nand_read_ll(unsigned char *buf, unsigned long start_addr, int size);
11
12 /* NAND Flash操作的总入口, 它们将调用S3C2410或S3C2440的相应函数 */
13 static void nand_reset(void);
14 static void wait_idle(void);
15 static void nand_select_chip(void);
16 static void nand_deselect_chip(void);
17 static void write_cmd(int cmd);
18 static void write_addr(unsigned int addr);
19 static unsigned char read_data(void);
20
21 /* S3C2410的NAND Flash处理函数 */
22 static void s3c2410_nand_reset(void);
23 static void s3c2410_wait_idle(void);
24 static void s3c2410_nand_select_chip(void);
25 static void s3c2410_nand_deselect_chip(void);
26 static void s3c2410_write_cmd(int cmd);
27 static void s3c2410_write_addr(unsigned int addr);
28 static unsigned char s3c2410_read_data(void);
29
30 /* S3C2440的NAND Flash处理函数 */
31 static void s3c2440_nand_reset(void);
32 static void s3c2440_wait_idle(void);
33 static void s3c2440_nand_select_chip(void);
34 static void s3c2440_nand_deselect_chip(void);
35 static void s3c2440_write_cmd(int cmd);
36 static void s3c2440_write_addr(unsigned int addr);
37 static unsigned char s3c2440_read_data(void);
38
39 /* S3C2410的NAND Flash操作函数 */
40
41 /* 复位 */
42 static void s3c2410_nand_reset(void)
43 {
44 s3c2410_nand_select_chip();
45 s3c2410_write_cmd(0xff); // 复位命令
46 s3c2410_wait_idle();
47 s3c2410_nand_deselect_chip();
48 }
49
50 /* 等待NAND Flash就绪 */
51 static void s3c2410_wait_idle(void)
52 {
53 int i;
54 S3C2410_NAND * s3c2410nand = (S3C2410_NAND *)0x4e000000;
55
56 volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFSTAT;
57 while(!(*p & BUSY))
58 for(i=0; i<10; i++);
59 }
60
61 /* 发出片选信号 */
62 static void s3c2410_nand_select_chip(void)
63 {
64 int i;
65 S3C2410_NAND * s3c2410nand = (S3C2410_NAND *)0x4e000000;
66
67 s3c2410nand->NFCONF &= ~(1<<11);
68 for(i=0; i<10; i++);
69 }
70
71 /* 取消片选信号 */
72 static void s3c2410_nand_deselect_chip(void)
73 {
74 S3C2410_NAND * s3c2410nand = (S3C2410_NAND *)0x4e000000;
75
76 s3c2410nand->NFCONF |= (1<<11);
77 }
78
79 /* 发出命令 */
80 static void s3c2410_write_cmd(int cmd)
81 {
82 S3C2410_NAND * s3c2410nand = (S3C2410_NAND *)0x4e000000;
83
84 volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFCMD;
85 *p = cmd;
86 }
87
88 /* 发出地址 */
89 static void s3c2410_write_addr(unsigned int addr)
90 {
91 int i;
92 S3C2410_NAND * s3c2410nand = (S3C2410_NAND *)0x4e000000;
93 volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFADDR;
94
95 *p = addr & 0xff;
96 for(i=0; i<10; i++);
97 *p = (addr >> 9) & 0xff;
98 for(i=0; i<10; i++);
99 *p = (addr >> 17) & 0xff;
100 for(i=0; i<10; i++);
101 *p = (addr >> 25) & 0xff;
102 for(i=0; i<10; i++);
103 }
104
105 /* 读取数据 */
106 static unsigned char s3c2410_read_data(void)
107 {
108 S3C2410_NAND * s3c2410nand = (S3C2410_NAND *)0x4e000000;
109
110 volatile unsigned char *p = (volatile unsigned char *)&s3c2410nand->NFDATA;
111 return *p;
112 }
113
114 /* S3C2440的NAND Flash操作函数 */
115
116 /* 复位 */
117 static void s3c2440_nand_reset(void)
118 {
119 s3c2440_nand_select_chip();
120 s3c2440_write_cmd(0xff); // 复位命令
121 s3c2440_wait_idle();
122 s3c2440_nand_deselect_chip();
123 }
124
125 /* 等待NAND Flash就绪 */
126 static void s3c2440_wait_idle(void)
127 {
128 int i;
129 S3C2440_NAND * s3c2440nand = (S3C2440_NAND *)0x4e000000;
130 volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFSTAT;
131
132 while(!(*p & BUSY))
133 for(i=0; i<10; i++);
134 }
135
136 /* 发出片选信号 */
137 static void s3c2440_nand_select_chip(void)
138 {
139 int i;
140 S3C2440_NAND * s3c2440nand = (S3C2440_NAND *)0x4e000000;
141
142 s3c2440nand->NFCONT &= ~(1<<1);
143 for(i=0; i<10; i++);
144 }
145
146 /* 取消片选信号 */
147 static void s3c2440_nand_deselect_chip(void)
148 {
149 S3C2440_NAND * s3c2440nand = (S3C2440_NAND *)0x4e000000;
150
151 s3c2440nand->NFCONT |= (1<<1);
152 }
153
154 /* 发出命令 */
155 static void s3c2440_write_cmd(int cmd)
156 {
157 S3C2440_NAND * s3c2440nand = (S3C2440_NAND *)0x4e000000;
158
159 volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFCMD;
160 *p = cmd;
161 }
162
163 /* 发出地址 */
164 static void s3c2440_write_addr(unsigned int addr)
165 {
166 int i;
167 S3C2440_NAND * s3c2440nand = (S3C2440_NAND *)0x4e000000;
168 volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFADDR;
169
170 *p = addr & 0xff;
171 for(i=0; i<10; i++);
172 *p = (addr >> 9) & 0xff;
173 for(i=0; i<10; i++);
174 *p = (addr >> 17) & 0xff;
175 for(i=0; i<10; i++);
176 *p = (addr >> 25) & 0xff;
177 for(i=0; i<10; i++);
178 }
179
180 /* 读取数据 */
181 static unsigned char s3c2440_read_data(void)
182 {
183 S3C2440_NAND * s3c2440nand = (S3C2440_NAND *)0x4e000000;
184 volatile unsigned char *p = (volatile unsigned char *)&s3c2440nand->NFDATA;
185 return *p;
186 }
187
188
189 /* 在第一次使用NAND Flash前，复位一下NAND Flash */
190 static void nand_reset(void)
191 {
192 /* 判断是S3C2410还是S3C2440 */
193 if ((GSTATUS1 == 0x32410000) || (GSTATUS1 == 0x32410002))
194 {
195 s3c2410_nand_reset();
196 }
197 else
198 {
199 s3c2440_nand_reset();
200 }
201 }
202
203 static void wait_idle(void)
204 {
205 /* 判断是S3C2410还是S3C2440 */
206 if ((GSTATUS1 == 0x32410000) || (GSTATUS1 == 0x32410002))
207 {
208 s3c2410_wait_idle();
209 }
210 else
211 {
212 s3c2440_wait_idle();
213 }
214 }
215
216 static void nand_select_chip(void)
217 {
218 int i;
219
220 /* 判断是S3C2410还是S3C2440 */
221 if ((GSTATUS1 == 0x32410000) || (GSTATUS1 == 0x32410002))
222 {
223 s3c2410_nand_select_chip();
224 }
225 else
226 {
227 s3c2440_nand_select_chip();
228 }
229
230 for(i=0; i<10; i++);
231 }
232
233 static void nand_deselect_chip(void)
234 {
235 /* 判断是S3C2410还是S3C2440 */
236 if ((GSTATUS1 == 0x32410000) || (GSTATUS1 == 0x32410002))
237 {
238 s3c2410_nand_deselect_chip();
239 }
240 else
241 {
242 s3c2440_nand_deselect_chip();
243 }
244 }
245
246 static void write_cmd(int cmd)
247 {
248 /* 判断是S3C2410还是S3C2440 */
249 if ((GSTATUS1 == 0x32410000) || (GSTATUS1 == 0x32410002))
250 {
251 s3c2410_write_cmd(cmd);
252 }
253 else
254 {
255 s3c2440_write_cmd(cmd);
256 }
257 }
258 static void write_addr(unsigned int addr)
259 {
260 /* 判断是S3C2410还是S3C2440 */
261 if ((GSTATUS1 == 0x32410000) || (GSTATUS1 == 0x32410002))
262 {
263 s3c2410_write_addr(addr);
264 }
265 else
266 {
267 s3c2440_write_addr(addr);
268 }
269 }
270
271 static unsigned char read_data(void)
272 {
273 /* 判断是S3C2410还是S3C2440 */
274 if ((GSTATUS1 == 0x32410000) || (GSTATUS1 == 0x32410002))
275 {
276 return s3c2410_read_data();
277 }
278 else
279 {
280 return s3c2440_read_data();
281 }
282 }
283
284 /* 初始化NAND Flash */
285 void nand_init_ll(void)
286 {
287 S3C2410_NAND * s3c2410nand = (S3C2410_NAND *)0x4e000000;
288 S3C2440_NAND * s3c2440nand = (S3C2440_NAND *)0x4e000000;
289
290 #define TACLS 0
291 #define TWRPH0 3
292 #define TWRPH1 0
293
294 /* 判断是S3C2410还是S3C2440 */
295 if ((GSTATUS1 == 0x32410000) || (GSTATUS1 == 0x32410002))
296 {
297 /* 使能NAND Flash控制器, 初始化ECC, 禁止片选, 设置时序 */
298 s3c2410nand->NFCONF = (1<<15)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0);
299 }
300 else
301 {
302 /* 设置时序 */
303 s3c2440nand->NFCONF = (TACLS<<12)|(TWRPH0<<8)|(TWRPH1<<4);
304 /* 使能NAND Flash控制器, 初始化ECC, 禁止片选 */
305 s3c2440nand->NFCONT = (1<<4)|(1<<1)|(1<<0);
306 }
307
308 /* 复位NAND Flash */
309 nand_reset();
310 }
311
312
313 #define NAND_SECTOR_SIZE 512
314 #define NAND_BLOCK_MASK (NAND_SECTOR_SIZE - 1)
315
316 /* 读函数 */
317 void nand_read_ll(unsigned char *buf, unsigned long start_addr, int size)
318 {
319 int i, j;
320
321 if ((start_addr & NAND_BLOCK_MASK) || (size & NAND_BLOCK_MASK)) {
322 return ; /* 地址或长度不对齐 */
323 }
324
325 /* 选中芯片 */
326 nand_select_chip();
327
328 for(i=start_addr; i < (start_addr + size);) {
329 /* 发出READ0命令 */
330 write_cmd(0);
331
332 /* Write Address */
333 write_addr(i);
334 wait_idle();
335
336 for(j=0; j < NAND_SECTOR_SIZE; j++, i++) {
337 *buf = read_data();
338 buf++;
339 }
340 }
341
342 /* 取消片选信号 */
343 nand_deselect_chip();
344
345 return ;
346 }
347
348 int bBootFrmNORFlash(void)
349 {
350 volatile unsigned int *pdw = (volatile unsigned int *)0;
351 unsigned int dwVal;
352
353 /*
354 * 无论是从NOR Flash还是从NAND Flash启动，
355 * 地址0处为指令"b Reset", 机器码为0xEA00000B，
356 * 对于从NAND Flash启动的情况，其开始4KB的代码会复制到CPU内部4K内存中，
357 * 对于从NOR Flash启动的情况，NOR Flash的开始地址即为0。
358 * 对于NOR Flash，必须通过一定的命令序列才能写数据，
359 * 所以可以根据这点差别来分辨是从NAND Flash还是NOR Flash启动:
360 * 向地址0写入一个数据，然后读出来，如果没有改变的话就是NOR Flash
361 */
362
363 dwVal = *pdw;
364 *pdw = 0x12345678;
365 if (*pdw != 0x12345678)
366 {
367 return 1;
368 }
369 else
370 {
371 *pdw = dwVal;
372 return 0;
373 }
374 }
375
376 int CopyCode2Ram(unsigned long start_addr, unsigned char *buf, int size)
377 {
378 unsigned int *pdwDest;
379 unsigned int *pdwSrc;
380 int i;
381
382 if (bBootFrmNORFlash())
383 {
384 pdwDest = (unsigned int *)buf;
385 pdwSrc = (unsigned int *)start_addr;
386 /* 从 NOR Flash启动 */
387 for (i = 0; i < size / 4; i++)
388 {
389 pdwDest[i] = pdwSrc[i];
390 }
391 return 0;
392 }
393 else
394 {
395 /* 初始化NAND Flash */
396 nand_init_ll();
397 /* 从 NAND Flash启动 */
398 nand_read_ll(buf, start_addr, (size + NAND_BLOCK_MASK)&~(NAND_BLOCK_MASK));
399 return 0;
400 }
401 }
402
403 static inline void delay (unsigned long loops)
404 {
405 __asm__ volatile ("1:/n"
406 "subs %0, %1, #1/n"
407 "bne 1b":"=r" (loops):"0" (loops));
408 }
409
410 /* S3C2440: Mpll = (2*m * Fin) / (p * 2^s), UPLL = (m * Fin) / (p * 2^s)
411 * m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2
412 */
413 #define S3C2440_MPLL_400MHZ ((0x5c<<12)|(0x01<<4)|(0x01))
414 #define S3C2440_MPLL_200MHZ ((0x5c<<12)|(0x01<<4)|(0x02))
415 #define S3C2440_MPLL_100MHZ ((0x5c<<12)|(0x01<<4)|(0x03))
416 #define S3C2440_UPLL_96MHZ ((0x38<<12)|(0x02<<4)|(0x01))
417 #define S3C2440_UPLL_48MHZ ((0x38<<12)|(0x02<<4)|(0x02))
418 #define S3C2440_CLKDIV (0x05) // | (1<<3)) /* FCLK:HCLK:PCLK = 1:4:8, UCLK = UPLL/2 */
419 #define S3C2440_CLKDIV188 0x04 /* FCLK:HCLK:PCLK = 1:8:8 */
420 #define S3C2440_CAMDIVN188 ((0<<8)|(1<<9)) /* FCLK:HCLK:PCLK = 1:8:8 */
421
422 /* S3C2410: Mpll,Upll = (m * Fin) / (p * 2^s)
423 * m = M (the value for divider M)+ 8, p = P (the value for divider P) + 2
424 */
425 #define S3C2410_MPLL_200MHZ ((0x5c<<12)|(0x04<<4)|(0x00))
426 #define S3C2410_UPLL_48MHZ ((0x28<<12)|(0x01<<4)|(0x02))
427 #define S3C2410_CLKDIV 0x03 /* FCLK:HCLK:PCLK = 1:2:4 */
428 void clock_init(void)
429 {
430 S3C24X0_CLOCK_POWER *clk_power = (S3C24X0_CLOCK_POWER *)0x4C000000;
431
432 /* support both of S3C2410 and S3C2440, by www.arm9.net */
433 if ((GSTATUS1 == 0x32410000) || (GSTATUS1 == 0x32410002))
434 {
435 /* FCLK:HCLK:PCLK = 1:2:4 */
436 clk_power->CLKDIVN = S3C2410_CLKDIV;
437
438 /* change to asynchronous bus mod */
439 __asm__( "mrc p15, 0, r1, c1, c0, 0/n" /* read ctrl register */
440 "orr r1, r1, #0xc0000000/n" /* Asynchronous */
441 "mcr p15, 0, r1, c1, c0, 0/n" /* write ctrl register */
442 :::"r1"
443 );
444
445 /* to reduce PLL lock time, adjust the LOCKTIME register */
446 clk_power->LOCKTIME = 0xFFFFFFFF;
447
448 /* configure UPLL */
449 clk_power->UPLLCON = S3C2410_UPLL_48MHZ;
450
451 /* some delay between MPLL and UPLL */
452 delay (4000);
453
454 /* configure MPLL */
455 clk_power->MPLLCON = S3C2410_MPLL_200MHZ;
456
457 /* some delay between MPLL and UPLL */
458 delay (8000);
459 }
460 else
461 {
462 /* FCLK:HCLK:PCLK = 1:4:8 */
463 clk_power->CLKDIVN = S3C2440_CLKDIV;
464
465 /* change to asynchronous bus mod */
466 __asm__( "mrc p15, 0, r1, c1, c0, 0/n" /* read ctrl register */
467 "orr r1, r1, #0xc0000000/n" /* Asynchronous */
468 "mcr p15, 0, r1, c1, c0, 0/n" /* write ctrl register */
469 :::"r1"
470 );
471
472 /* to reduce PLL lock time, adjust the LOCKTIME register */
473 clk_power->LOCKTIME = 0xFFFFFFFF;
474
475 /* configure UPLL */
476 clk_power->UPLLCON = S3C2440_UPLL_48MHZ;
477
478 /* some delay between MPLL and UPLL */
479 delay (4000);
480
481 /* configure MPLL */
482 clk_power->MPLLCON = S3C2440_MPLL_400MHZ;
483
484 /* some delay between MPLL and UPLL */
485 delay (8000);
486 }
487 }
488
////////////
新引入s3c2410a.h 放到include下, 内容如下，不需任何修改
include/s3c2410a.h
1 /*
2 * (C) Copyright 2003
3 * David M黮ler ELSOFT AG Switzerland. [email protected]
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /************************************************
25 * NAME : s3c2410.h
26 * Version : 31.3.2003
27 *
28 * Based on S3C2410X User's manual Rev 1.1
29 ************************************************/
30
31 #ifndef __S3C2410_H__
32 #define __S3C2410_H__
33
34 #define S3C24X0_UART_CHANNELS 3
35 #define S3C24X0_SPI_CHANNELS 2
36
37 /* S3C2410 only supports 512 Byte HW ECC */
38 #define S3C2410_ECCSIZE 512
39 #define S3C2410_ECCBYTES 3
40
41 typedef enum {
42 S3C24X0_UART0,
43 S3C24X0_UART1,
44 S3C24X0_UART2
45 } S3C24X0_UARTS_NR;
46
47 /* S3C2410 device base addresses */
48 #define S3C24X0_MEMCTL_BASE 0x48000000
49 #define S3C24X0_USB_HOST_BASE 0x49000000
50 #define S3C24X0_INTERRUPT_BASE 0x4A000000
51 #define S3C24X0_DMA_BASE 0x4B000000
52 #define S3C24X0_CLOCK_POWER_BASE 0x4C000000
53 #define S3C24X0_LCD_BASE 0x4D000000
54 #define S3C2410_NAND_BASE 0x4E000000
55 #define S3C24X0_UART_BASE 0x50000000
56 #define S3C24X0_TIMER_BASE 0x51000000
57 #define S3C24X0_USB_DEVICE_BASE 0x52000140
58 #define S3C24X0_WATCHDOG_BASE 0x53000000
59 #define S3C24X0_I2C_BASE 0x54000000
60 #define S3C24X0_I2S_BASE 0x55000000
61 #define S3C24X0_GPIO_BASE 0x56000000
62 #define S3C24X0_RTC_BASE 0x57000000
63 #define S3C2410_ADC_BASE 0x58000000
64 #define S3C24X0_SPI_BASE 0x59000000
65 #define S3C2410_SDI_BASE 0x5A000000
66
67
68 /* include common stuff */
69 #include
70
71
72 static inline S3C24X0_MEMCTL * const S3C24X0_GetBase_MEMCTL(void)
73 {
74 return (S3C24X0_MEMCTL * const)S3C24X0_MEMCTL_BASE;
75 }
76 static inline S3C24X0_USB_HOST * const S3C24X0_GetBase_USB_HOST(void)
77 {
78 return (S3C24X0_USB_HOST * const)S3C24X0_USB_HOST_BASE;
79 }
80 static inline S3C24X0_INTERRUPT * const S3C24X0_GetBase_INTERRUPT(void)
81 {
82 return (S3C24X0_INTERRUPT * const)S3C24X0_INTERRUPT_BASE;
83 }
84 static inline S3C24X0_DMAS * const S3C24X0_GetBase_DMAS(void)
85 {
86 return (S3C24X0_DMAS * const)S3C24X0_DMA_BASE;
87 }
88 static inline S3C24X0_CLOCK_POWER * const S3C24X0_GetBase_CLOCK_POWER(void)
89 {
90 return (S3C24X0_CLOCK_POWER * const)S3C24X0_CLOCK_POWER_BASE;
91 }
92 static inline S3C24X0_LCD * const S3C24X0_GetBase_LCD(void)
93 {
94 return (S3C24X0_LCD * const)S3C24X0_LCD_BASE;
95 }
96 static inline S3C2410_NAND * const S3C2410_GetBase_NAND(void)
97 {
98 return (S3C2410_NAND * const)S3C2410_NAND_BASE;
99 }
100
101 /* for s3c2440, www.arm9.net */
102 static inline S3C2440_NAND * const S3C2440_GetBase_NAND(void)
103 {
104 return (S3C2440_NAND * const)S3C2410_NAND_BASE;
105 }
106 static inline S3C24X0_UART * const S3C24X0_GetBase_UART(S3C24X0_UARTS_NR nr)
107 {
108 return (S3C24X0_UART * const)(S3C24X0_UART_BASE + (nr * 0x4000));
109 }
110 static inline S3C24X0_TIMERS * const S3C24X0_GetBase_TIMERS(void)
111 {
112 return (S3C24X0_TIMERS * const)S3C24X0_TIMER_BASE;
113 }
114 static inline S3C24X0_USB_DEVICE * const S3C24X0_GetBase_USB_DEVICE(void)
115 {
116 return (S3C24X0_USB_DEVICE * const)S3C24X0_USB_DEVICE_BASE;
117 }
118 static inline S3C24X0_WATCHDOG * const S3C24X0_GetBase_WATCHDOG(void)
119 {
120 return (S3C24X0_WATCHDOG * const)S3C24X0_WATCHDOG_BASE;
121 }
122 static inline S3C24X0_I2C * const S3C24X0_GetBase_I2C(void)
123 {
124 return (S3C24X0_I2C * const)S3C24X0_I2C_BASE;
125 }
126 static inline S3C24X0_I2S * const S3C24X0_GetBase_I2S(void)
127 {
128 return (S3C24X0_I2S * const)S3C24X0_I2S_BASE;
129 }
130 static inline S3C24X0_GPIO * const S3C24X0_GetBase_GPIO(void)
131 {
132 return (S3C24X0_GPIO * const)S3C24X0_GPIO_BASE;
133 }
134 static inline S3C24X0_RTC * const S3C24X0_GetBase_RTC(void)
135 {
136 return (S3C24X0_RTC * const)S3C24X0_RTC_BASE;
137 }
138 static inline S3C2410_ADC * const S3C2410_GetBase_ADC(void)
139 {
140 return (S3C2410_ADC * const)S3C2410_ADC_BASE;
141 }
142 static inline S3C24X0_SPI * const S3C24X0_GetBase_SPI(void)
143 {
144 return (S3C24X0_SPI * const)S3C24X0_SPI_BASE;
145 }
146 static inline S3C2410_SDI * const S3C2410_GetBase_SDI(void)
147 {
148 return (S3C2410_SDI * const)S3C2410_SDI_BASE;
149 }
150
151 /* add by mike.arm9 */
152 #define _ISR_STARTADDRESS ((unsigned)isr_handle_array)
153
154 #define ISR_EINT0_OFT 0
155 #define ISR_EINT1_OFT 1
156 #define ISR_EINT2_OFT 2
157 #define ISR_EINT3_OFT 3
158 #define ISR_EINT4_7_OFT 4
159 #define ISR_EINT8_23_OFT 5
160 #define ISR_NOTUSED6_OFT 6
161 #define ISR_BAT_FLT_OFT 7
162 #define ISR_TICK_OFT 8
163 #define ISR_WDT_OFT 9
164 #define ISR_TIMER0_OFT 10
165 #define ISR_TIMER1_OFT 11
166 #define ISR_TIMER2_OFT 12
167 #define ISR_TIMER3_OFT 13
168 #define ISR_TIMER4_OFT 14
169 #define ISR_UART2_OFT 15
170 #define ISR_LCD_OFT 16
171 #define ISR_DMA0_OFT 17
172 #define ISR_DMA1_OFT 18
173 #define ISR_DMA2_OFT 19
174 #define ISR_DMA3_OFT 20
175 #define ISR_SDI_OFT 21
176 #define ISR_SPI0_OFT 22
177 #define ISR_UART1_OFT 23
178 #define ISR_NOTUSED24_OFT 24
179 #define ISR_USBD_OFT 25
180 #define ISR_USBH_OFT 26
181 #define ISR_IIC_OFT 27
182 #define ISR_UART0_OFT 28
183 #define ISR_SPI1_OFT 29
184 #define ISR_RTC_OFT 30
185 #define ISR_ADC_OFT 31
186
187 /* ISR */
188 #define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
189 #define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
190 #define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
191 #define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xC))
192 #define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
193 #define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
194 #define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
195 #define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1C))
196
197 #define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
198 #define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
199 #define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
200 #define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2C))
201 #define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
202 #define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
203 #define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3C))
204 #define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
205 #define pISR_WDT (*(unsigned *)(_ISR_STARTADDRESS+0x44))
206 #define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
207 #define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4C))
208 #define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
209 #define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
210 #define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
211 #define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5C))
212 #define pISR_NOTUSED (*(unsigned *)(_ISR_STARTADDRESS+0x60))
213 #define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
214 #define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
215 #define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6C))
216 #define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
217 #define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
218 #define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
219 #define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7C))
220 #define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
221 #define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
222 #define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8C))
223 #define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
224 #define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
225 #define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
226 #define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0xA0))
227
228
229 // PENDING BIT
230 #define BIT_EINT0 (0x1)
231 #define BIT_EINT1 (0x1<<1)
232 #define BIT_EINT2 (0x1<<2)
233 #define BIT_EINT3 (0x1<<3)
234 #define BIT_EINT4_7 (0x1<<4)
235 #define BIT_EINT8_23 (0x1<<5)
236 #define BIT_CAM (0x1<<6) // Added for 2440.
237 #define BIT_BAT_FLT (0x1<<7)
238 #define BIT_TICK (0x1<<8)
239 #define BIT_WDT_AC97 (0x1<<9)
240 #define BIT_TIMER0 (0x1<<10)
241 #define BIT_TIMER1 (0x1<<11)
242 #define BIT_TIMER2 (0x1<<12)
243 #define BIT_TIMER3 (0x1<<13)
244 #define BIT_TIMER4 (0x1<<14)
245 #define BIT_UART2 (0x1<<15)
246 #define BIT_LCD (0x1<<16)
247 #define BIT_DMA0 (0x1<<17)
248 #define BIT_DMA1 (0x1<<18)
249 #define BIT_DMA2 (0x1<<19)
250 #define BIT_DMA3 (0x1<<20)
251 #define BIT_SDI (0x1<<21)
252 #define BIT_SPI0 (0x1<<22)
253 #define BIT_UART1 (0x1<<23)
254 #define BIT_NFCON (0x1<<24) // Added for 2440.
255 #define BIT_USBD (0x1<<25)
256 #define BIT_USBH (0x1<<26)
257 #define BIT_IIC (0x1<<27)
258 #define BIT_UART0 (0x1<<28)
259 #define BIT_SPI1 (0x1<<29)
260 #define BIT_RTC (0x1<<30)
261 #define BIT_ADC (0x1<<31)
262 #define BIT_ALLMSK (0xffffffff)
263
264 #define BIT_SUB_ALLMSK (0x7fff)
265 #define BIT_SUB_AC97 (0x1<<14)
266 #define BIT_SUB_WDT (0x1<<13)
267 #define BIT_SUB_CAM_S (0x1<<12) // Added for 2440.
268 #define BIT_SUB_CAM_C (0x1<<11) // Added for 2440.
269 #define BIT_SUB_ADC (0x1<<10)
270 #define BIT_SUB_TC (0x1<<9)
271 #define BIT_SUB_ERR2 (0x1<<8)
272 #define BIT_SUB_TXD2 (0x1<<7)
273 #define BIT_SUB_RXD2 (0x1<<6)
274 #define BIT_SUB_ERR1 (0x1<<5)
275 #define BIT_SUB_TXD1 (0x1<<4)
276 #define BIT_SUB_RXD1 (0x1<<3)
277 #define BIT_SUB_ERR0 (0x1<<2)
278 #define BIT_SUB_TXD0 (0x1<<1)
279 #define BIT_SUB_RXD0 (0x1<<0)
280
281 #endif /*__S3C2410_H__*/
//////////////
include/s3c24x0.h 为新的引入的文件，内容如下：并做少许修改
1 /*
2 * (C) Copyright 2003
3 * David M黮ler ELSOFT AG Switzerland. [email protected]
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /************************************************
25 * NAME : s3c24x0.h
26 * Version : 31.3.2003
27 *
28 * common stuff for SAMSUNG S3C24X0 SoC
29 ************************************************/
30
31 #ifndef __S3C24X0_H__
32 #define __S3C24X0_H__
33 #include "types.h" // snallie
/* 33行为新加入的，包含types.h ，types.h无需新引入，ARMboot的源码目录中含有该文件 */
34
35 typedef volatile u8 S3C24X0_REG8;
36 typedef volatile u16 S3C24X0_REG16;
37 typedef volatile u32 S3C24X0_REG32;
38
39 /* Memory controller (see manual chapter 5) */
40 typedef struct {
41 S3C24X0_REG32 BWSCON;
42 S3C24X0_REG32 BANKCON[8];
43 S3C24X0_REG32 REFRESH;
44 S3C24X0_REG32 BANKSIZE;
45 S3C24X0_REG32 MRSRB6;
46 S3C24X0_REG32 MRSRB7;
47 } /*__attribute__((__packed__))*/ S3C24X0_MEMCTL;
48
49
50 /* USB HOST (see manual chapter 12) */
51 typedef struct {
52 S3C24X0_REG32 HcRevision;
53 S3C24X0_REG32 HcControl;
54 S3C24X0_REG32 HcCommonStatus;
55 S3C24X0_REG32 HcInterruptStatus;
56 S3C24X0_REG32 HcInterruptEnable;
57 S3C24X0_REG32 HcInterruptDisable;
58 S3C24X0_REG32 HcHCCA;
59 S3C24X0_REG32 HcPeriodCuttendED;
60 S3C24X0_REG32 HcControlHeadED;
61 S3C24X0_REG32 HcControlCurrentED;
62 S3C24X0_REG32 HcBulkHeadED;
63 S3C24X0_REG32 HcBuldCurrentED;
64 S3C24X0_REG32 HcDoneHead;
65 S3C24X0_REG32 HcRmInterval;
66 S3C24X0_REG32 HcFmRemaining;
67 S3C24X0_REG32 HcFmNumber;
68 S3C24X0_REG32 HcPeriodicStart;
69 S3C24X0_REG32 HcLSThreshold;
70 S3C24X0_REG32 HcRhDescriptorA;
71 S3C24X0_REG32 HcRhDescriptorB;
72 S3C24X0_REG32 HcRhStatus;
73 S3C24X0_REG32 HcRhPortStatus1;
74 S3C24X0_REG32 HcRhPortStatus2;
75 } /*__attribute__((__packed__))*/ S3C24X0_USB_HOST;
76
77
78 /* INTERRUPT (see manual chapter 14) */
79 typedef struct {
80 S3C24X0_REG32 SRCPND;
81 S3C24X0_REG32 INTMOD;
82 S3C24X0_REG32 INTMSK;
83 S3C24X0_REG32 PRIORITY;
84 S3C24X0_REG32 INTPND;
85 S3C24X0_REG32 INTOFFSET;
86 #ifdef CONFIG_S3C2410
87 S3C24X0_REG32 SUBSRCPND;
88 S3C24X0_REG32 INTSUBMSK;
89 #endif
90 } /*__attribute__((__packed__))*/ S3C24X0_INTERRUPT;
91
92
93 /* DMAS (see manual chapter 8) */
94 typedef struct {
95 S3C24X0_REG32 DISRC;
96 #ifdef CONFIG_S3C2410
97 S3C24X0_REG32 DISRCC;
98 #endif
99 S3C24X0_REG32 DIDST;
100 #ifdef CONFIG_S3C2410
101 S3C24X0_REG32 DIDSTC;
102 #endif
103 S3C24X0_REG32 DCON;
104 S3C24X0_REG32 DSTAT;
105 S3C24X0_REG32 DCSRC;
106 S3C24X0_REG32 DCDST;
107 S3C24X0_REG32 DMASKTRIG;
108 #ifdef CONFIG_S3C2400
109 S3C24X0_REG32 res[1];
110 #endif
111 #ifdef CONFIG_S3C2410
112 S3C24X0_REG32 res[7];
113 #endif
114 } /*__attribute__((__packed__))*/ S3C24X0_DMA;
115
116 typedef struct {
117 S3C24X0_DMA dma[4];
118 } /*__attribute__((__packed__))*/ S3C24X0_DMAS;
119
120
121 /* CLOCK & POWER MANAGEMENT (see S3C2400 manual chapter 6) */
122 /* (see S3C2410 manual chapter 7) */
123 typedef struct {
124 S3C24X0_REG32 LOCKTIME;
125 S3C24X0_REG32 MPLLCON;
126 S3C24X0_REG32 UPLLCON;
127 S3C24X0_REG32 CLKCON;
128 S3C24X0_REG32 CLKSLOW;
129 S3C24X0_REG32 CLKDIVN;
130 S3C24X0_REG32 CAMDIVN; /* for s3c2440, by www.arm9.net */
131 } /*__attribute__((__packed__))*/ S3C24X0_CLOCK_POWER;
132
133
134 /* LCD CONTROLLER (see manual chapter 15) */
135 typedef struct {
136 S3C24X0_REG32 LCDCON1;
137 S3C24X0_REG32 LCDCON2;
138 S3C24X0_REG32 LCDCON3;
139 S3C24X0_REG32 LCDCON4;
140 S3C24X0_REG32 LCDCON5;
141 S3C24X0_REG32 LCDSADDR1;
142 S3C24X0_REG32 LCDSADDR2;
143 S3C24X0_REG32 LCDSADDR3;
144 S3C24X0_REG32 REDLUT;
145 S3C24X0_REG32 GREENLUT;
146 S3C24X0_REG32 BLUELUT;
147 S3C24X0_REG32 res[8];
148 S3C24X0_REG32 DITHMODE;
149 S3C24X0_REG32 TPAL;
150 #ifdef CONFIG_S3C2410
151 S3C24X0_REG32 LCDINTPND;
152 S3C24X0_REG32 LCDSRCPND;
153 S3C24X0_REG32 LCDINTMSK;
154 S3C24X0_REG32 LPCSEL;
155 #endif
156 } /*__attribute__((__packed__))*/ S3C24X0_LCD;
157
158
159 /* NAND FLASH (see S3C2410 manual chapter 6) */
160 typedef struct {
161 S3C24X0_REG32 NFCONF;
162 S3C24X0_REG32 NFCMD;
163 S3C24X0_REG32 NFADDR;
164 S3C24X0_REG32 NFDATA;
165 S3C24X0_REG32 NFSTAT;
166 S3C24X0_REG32 NFECC;
167 } /*__attribute__((__packed__))*/ S3C2410_NAND;
168
169 /* NAND FLASH (see S3C2440 manual chapter 6, www.arm9.net) */
170 typedef struct {
171 S3C24X0_REG32 NFCONF;
172 S3C24X0_REG32 NFCONT;
173 S3C24X0_REG32 NFCMD;
174 S3C24X0_REG32 NFADDR;
175 S3C24X0_REG32 NFDATA;
176 S3C24X0_REG32 NFMECCD0;
177 S3C24X0_REG32 NFMECCD1;
178 S3C24X0_REG32 NFSECCD;
179 S3C24X0_REG32 NFSTAT;
180 S3C24X0_REG32 NFESTAT0;
181 S3C24X0_REG32 NFESTAT1;
182 S3C24X0_REG32 NFMECC0;
183 S3C24X0_REG32 NFMECC1;
184 S3C24X0_REG32 NFSECC;
185 S3C24X0_REG32 NFSBLK;
186 S3C24X0_REG32 NFEBLK;
187 } /*__attribute__((__packed__))*/ S3C2440_NAND;
188
189 /* UART (see manual chapter 11) */
190 typedef struct {
191 S3C24X0_REG32 ULCON;
192 S3C24X0_REG32 UCON;
193 S3C24X0_REG32 UFCON;
194 S3C24X0_REG32 UMCON;
195 S3C24X0_REG32 UTRSTAT;
196 S3C24X0_REG32 UERSTAT;
197 S3C24X0_REG32 UFSTAT;
198 S3C24X0_REG32 UMSTAT;
199 #ifdef __BIG_ENDIAN
200 S3C24X0_REG8 res1[3];
201 S3C24X0_REG8 UTXH;
202 S3C24X0_REG8 res2[3];
203 S3C24X0_REG8 URXH;
204 #else /* Little Endian */
205 S3C24X0_REG8 UTXH;
206 S3C24X0_REG8 res1[3];
207 S3C24X0_REG8 URXH;
208 S3C24X0_REG8 res2[3];
209 #endif
210 S3C24X0_REG32 UBRDIV;
211 } /*__attribute__((__packed__))*/ S3C24X0_UART;
212
213
214 /* PWM TIMER (see manual chapter 10) */
215 typedef struct {
216 S3C24X0_REG32 TCNTB;
217 S3C24X0_REG32 TCMPB;
218 S3C24X0_REG32 TCNTO;
219 } /*__attribute__((__packed__))*/ S3C24X0_TIMER;
220
221 typedef struct {
222 S3C24X0_REG32 TCFG0;
223 S3C24X0_REG32 TCFG1;
224 S3C24X0_REG32 TCON;
225 S3C24X0_TIMER ch[4];
226 S3C24X0_REG32 TCNTB4;
227 S3C24X0_REG32 TCNTO4;
228 } /*__attribute__((__packed__))*/ S3C24X0_TIMERS;
229
230
231 /* USB DEVICE (see manual chapter 13) */
232 typedef struct {
233 #ifdef __BIG_ENDIAN
234 S3C24X0_REG8 res[3];
235 S3C24X0_REG8 EP_FIFO_REG;
236 #else /* little endian */
237 S3C24X0_REG8 EP_FIFO_REG;
238 S3C24X0_REG8 res[3];
239 #endif
240 } /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_FIFOS;
241
242 typedef struct {
243 #ifdef __BIG_ENDIAN
244 S3C24X0_REG8 res1[3];
245 S3C24X0_REG8 EP_DMA_CON;
246 S3C24X0_REG8 res2[3];
247 S3C24X0_REG8 EP_DMA_UNIT;
248 S3C24X0_REG8 res3[3];
249 S3C24X0_REG8 EP_DMA_FIFO;
250 S3C24X0_REG8 res4[3];
251 S3C24X0_REG8 EP_DMA_TTC_L;
252 S3C24X0_REG8 res5[3];
253 S3C24X0_REG8 EP_DMA_TTC_M;
254 S3C24X0_REG8 res6[3];
255 S3C24X0_REG8 EP_DMA_TTC_H;
256 #else /* little endian */
257 S3C24X0_REG8 EP_DMA_CON;
258 S3C24X0_REG8 res1[3];
259 S3C24X0_REG8 EP_DMA_UNIT;
260 S3C24X0_REG8 res2[3];
261 S3C24X0_REG8 EP_DMA_FIFO;
262 S3C24X0_REG8 res3[3];
263 S3C24X0_REG8 EP_DMA_TTC_L;
264 S3C24X0_REG8 res4[3];
265 S3C24X0_REG8 EP_DMA_TTC_M;
266 S3C24X0_REG8 res5[3];
267 S3C24X0_REG8 EP_DMA_TTC_H;
268 S3C24X0_REG8 res6[3];
269 #endif
270 } /*__attribute__((__packed__))*/ S3C24X0_USB_DEV_DMAS;
271
272 typedef struct {
273 #ifdef __BIG_ENDIAN
274 S3C24X0_REG8 res1[3];
275 S3C24X0_REG8 FUNC_ADDR_REG;
276 S3C24X0_REG8 res2[3];
277 S3C24X0_REG8 PWR_REG;
278 S3C24X0_REG8 res3[3];
279 S3C24X0_REG8 EP_INT_REG;
280 S3C24X0_REG8 res4[15];
281 S3C24X0_REG8 USB_INT_REG;
282 S3C24X0_REG8 res5[3];
283 S3C24X0_REG8 EP_INT_EN_REG;
284 S3C24X0_REG8 res6[15];
285 S3C24X0_REG8 USB_INT_EN_REG;
286 S3C24X0_REG8 res7[3];
287 S3C24X0_REG8 FRAME_NUM1_REG;
288 S3C24X0_REG8 res8[3];
289 S3C24X0_REG8 FRAME_NUM2_REG;
290 S3C24X0_REG8 res9[3];
291 S3C24X0_REG8 INDEX_REG;
292 S3C24X0_REG8 res10[7];
293 S3C24X0_REG8 MAXP_REG;
294 S3C24X0_REG8 res11[3];
295 S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
296 S3C24X0_REG8 res12[3];
297 S3C24X0_REG8 IN_CSR2_REG;
298 S3C24X0_REG8 res13[7];
299 S3C24X0_REG8 OUT_CSR1_REG;
300 S3C24X0_REG8 res14[3];
301 S3C24X0_REG8 OUT_CSR2_REG;
302 S3C24X0_REG8 res15[3];
303 S3C24X0_REG8 OUT_FIFO_CNT1_REG;
304 S3C24X0_REG8 res16[3];
305 S3C24X0_REG8 OUT_FIFO_CNT2_REG;
306 #else /* little endian */
307 S3C24X0_REG8 FUNC_ADDR_REG;
308 S3C24X0_REG8 res1[3];
309 S3C24X0_REG8 PWR_REG;
310 S3C24X0_REG8 res2[3];
311 S3C24X0_REG8 EP_INT_REG;
312 S3C24X0_REG8 res3[15];
313 S3C24X0_REG8 USB_INT_REG;
314 S3C24X0_REG8 res4[3];
315 S3C24X0_REG8 EP_INT_EN_REG;
316 S3C24X0_REG8 res5[15];
317 S3C24X0_REG8 USB_INT_EN_REG;
318 S3C24X0_REG8 res6[3];
319 S3C24X0_REG8 FRAME_NUM1_REG;
320 S3C24X0_REG8 res7[3];
321 S3C24X0_REG8 FRAME_NUM2_REG;
322 S3C24X0_REG8 res8[3];
323 S3C24X0_REG8 INDEX_REG;
324 S3C24X0_REG8 res9[7];
325 S3C24X0_REG8 MAXP_REG;
326 S3C24X0_REG8 res10[3];
327 S3C24X0_REG8 EP0_CSR_IN_CSR1_REG;
328 S3C24X0_REG8 res11[3];
329 S3C24X0_REG8 IN_CSR2_REG;
330 S3C24X0_REG8 res12[7];
331 S3C24X0_REG8 OUT_CSR1_REG;
332 S3C24X0_REG8 res13[3];
333 S3C24X0_REG8 OUT_CSR2_REG;
334 S3C24X0_REG8 res14[3];
335 S3C24X0_REG8 OUT_FIFO_CNT1_REG;
336 S3C24X0_REG8 res15[3];
337 S3C24X0_REG8 OUT_FIFO_CNT2_REG;
338 S3C24X0_REG8 res16[3];
339 #endif /* __BIG_ENDIAN */
340 S3C24X0_REG32 res17[8];
341 S3C24X0_USB_DEV_FIFOS fifo[5];
342 S3C24X0_REG32 res18[11];
343 S3C24X0_USB_DEV_DMAS ep1;
344 S3C24X0_USB_DEV_DMAS ep2;
345 S3C24X0_REG8 res19[16];
346 S3C24X0_USB_DEV_DMAS ep3;
347 S3C24X0_USB_DEV_DMAS ep4;
348 } /*__attribute__((__packed__))*/ S3C24X0_USB_DEVICE;
349
350
351 /* WATCH DOG TIMER (see manual chapter 18) */
352 typedef struct {
353 S3C24X0_REG32 WTCON;
354 S3C24X0_REG32 WTDAT;
355 S3C24X0_REG32 WTCNT;
356 } /*__attribute__((__packed__))*/ S3C24X0_WATCHDOG;
357
358
359 /* IIC (see manual chapter 20) */
360 typedef struct {
361 S3C24X0_REG32 IICCON;
362 S3C24X0_REG32 IICSTAT;
363 S3C24X0_REG32 IICADD;
364 S3C24X0_REG32 IICDS;
365 } /*__attribute__((__packed__))*/ S3C24X0_I2C;
366
367
368 /* IIS (see manual chapter 21) */
369 typedef struct {
370 #ifdef __BIG_ENDIAN
371 S3C24X0_REG16 res1;
372 S3C24X0_REG16 IISCON;
373 S3C24X0_REG16 res2;
374 S3C24X0_REG16 IISMOD;
375 S3C24X0_REG16 res3;
376 S3C24X0_REG16 IISPSR;
377 S3C24X0_REG16 res4;
378 S3C24X0_REG16 IISFCON;
379 S3C24X0_REG16 res5;
380 S3C24X0_REG16 IISFIFO;
381 #else /* little endian */
382 S3C24X0_REG16 IISCON;
383 S3C24X0_REG16 res1;
384 S3C24X0_REG16 IISMOD;
385 S3C24X0_REG16 res2;
386 S3C24X0_REG16 IISPSR;
387 S3C24X0_REG16 res3;
388 S3C24X0_REG16 IISFCON;
389 S3C24X0_REG16 res4;
390 S3C24X0_REG16 IISFIFO;
391 S3C24X0_REG16 res5;
392 #endif
393 } /*__attribute__((__packed__))*/ S3C24X0_I2S;
394
395
396 /* I/O PORT (see manual chapter 9) */
397 typedef struct {
398 #ifdef CONFIG_S3C2400
399 S3C24X0_REG32 PACON;
400 S3C24X0_REG32 PADAT;
401
402 S3C24X0_REG32 PBCON;
403 S3C24X0_REG32 PBDAT;
404 S3C24X0_REG32 PBUP;
405
406 S3C24X0_REG32 PCCON;
407 S3C24X0_REG32 PCDAT;
408 S3C24X0_REG32 PCUP;
409
410 S3C24X0_REG32 PDCON;
411 S3C24X0_REG32 PDDAT;
412 S3C24X0_REG32 PDUP;
413
414 S3C24X0_REG32 PECON;
415 S3C24X0_REG32 PEDAT;
416 S3C24X0_REG32 PEUP;
417
418 S3C24X0_REG32 PFCON;
419 S3C24X0_REG32 PFDAT;
420 S3C24X0_REG32 PFUP;
421
422 S3C24X0_REG32 PGCON;
423 S3C24X0_REG32 PGDAT;
424 S3C24X0_REG32 PGUP;
425
426 S3C24X0_REG32 OPENCR;
427
428 S3C24X0_REG32 MISCCR;
429 S3C24X0_REG32 EXTINT;
430 #endif
431 #ifdef CONFIG_S3C2410
432 S3C24X0_REG32 GPACON;
433 S3C24X0_REG32 GPADAT;
434 S3C24X0_REG32 res1[2];
435 S3C24X0_REG32 GPBCON;
436 S3C24X0_REG32 GPBDAT;
437 S3C24X0_REG32 GPBUP;
438 S3C24X0_REG32 res2;
439 S3C24X0_REG32 GPCCON;
440 S3C24X0_REG32 GPCDAT;
441 S3C24X0_REG32 GPCUP;
442 S3C24X0_REG32 res3;
443 S3C24X0_REG32 GPDCON;
444 S3C24X0_REG32 GPDDAT;
445 S3C24X0_REG32 GPDUP;
446 S3C24X0_REG32 res4;
447 S3C24X0_REG32 GPECON;
448 S3C24X0_REG32 GPEDAT;
449 S3C24X0_REG32 GPEUP;
450 S3C24X0_REG32 res5;
451 S3C24X0_REG32 GPFCON;
452 S3C24X0_REG32 GPFDAT;
453 S3C24X0_REG32 GPFUP;
454 S3C24X0_REG32 res6;
455 S3C24X0_REG32 GPGCON;
456 S3C24X0_REG32 GPGDAT;
457 S3C24X0_REG32 GPGUP;
458 S3C24X0_REG32 res7;
459 S3C24X0_REG32 GPHCON;
460 S3C24X0_REG32 GPHDAT;
461 S3C24X0_REG32 GPHUP;
462 S3C24X0_REG32 res8;
463
464 S3C24X0_REG32 MISCCR;
465 S3C24X0_REG32 DCLKCON;
466 S3C24X0_REG32 EXTINT0;
467 S3C24X0_REG32 EXTINT1;
468 S3C24X0_REG32 EXTINT2;
469 S3C24X0_REG32 EINTFLT0;
470 S3C24X0_REG32 EINTFLT1;
471 S3C24X0_REG32 EINTFLT2;
472 S3C24X0_REG32 EINTFLT3;
473 S3C24X0_REG32 EINTMASK;
474 S3C24X0_REG32 EINTPEND;
475 S3C24X0_REG32 GSTATUS0;
476 S3C24X0_REG32 GSTATUS1;
477 S3C24X0_REG32 GSTATUS2;
478 S3C24X0_REG32 GSTATUS3;
479 S3C24X0_REG32 GSTATUS4;
480
481 /* s3c2440 */
482 S3C24X0_REG32 res9[4];
483 S3C24X0_REG32 GPJCON;
484 S3C24X0_REG32 GPJDAT;
485 S3C24X0_REG32 GPJUP;
486 #endif
487 } /*__attribute__((__packed__))*/ S3C24X0_GPIO;
488
489
490 /* RTC (see manual chapter 17) */
491 typedef struct {
492 #ifdef __BIG_ENDIAN
493 S3C24X0_REG8 res1[67];
494 S3C24X0_REG8 RTCCON;
495 S3C24X0_REG8 res2[3];
496 S3C24X0_REG8 TICNT;
497 S3C24X0_REG8 res3[11];
498 S3C24X0_REG8 RTCALM;
499 S3C24X0_REG8 res4[3];
500 S3C24X0_REG8 ALMSEC;
501 S3C24X0_REG8 res5[3];
502 S3C24X0_REG8 ALMMIN;
503 S3C24X0_REG8 res6[3];
504 S3C24X0_REG8 ALMHOUR;
505 S3C24X0_REG8 res7[3];
506 S3C24X0_REG8 ALMDATE;
507 S3C24X0_REG8 res8[3];
508 S3C24X0_REG8 ALMMON;
509 S3C24X0_REG8 res9[3];
510 S3C24X0_REG8 ALMYEAR;
511 S3C24X0_REG8 res10[3];
512 S3C24X0_REG8 RTCRST;
513 S3C24X0_REG8 res11[3];
514 S3C24X0_REG8 BCDSEC;
515 S3C24X0_REG8 res12[3];
516 S3C24X0_REG8 BCDMIN;
517 S3C24X0_REG8 res13[3];
518 S3C24X0_REG8 BCDHOUR;
519 S3C24X0_REG8 res14[3];
520 S3C24X0_REG8 BCDDATE;
521 S3C24X0_REG8 res15[3];
522 S3C24X0_REG8 BCDDAY;
523 S3C24X0_REG8 res16[3];
524 S3C24X0_REG8 BCDMON;
525 S3C24X0_REG8 res17[3];
526 S3C24X0_REG8 BCDYEAR;
527 #else /* little endian */
528 S3C24X0_REG8 res0[64];
529 S3C24X0_REG8 RTCCON;
530 S3C24X0_REG8 res1[3];
531 S3C24X0_REG8 TICNT;
532 S3C24X0_REG8 res2[11];
533 S3C24X0_REG8 RTCALM;
534 S3C24X0_REG8 res3[3];
535 S3C24X0_REG8 ALMSEC;
536 S3C24X0_REG8 res4[3];
537 S3C24X0_REG8 ALMMIN;
538 S3C24X0_REG8 res5[3];
539 S3C24X0_REG8 ALMHOUR;
540 S3C24X0_REG8 res6[3];
541 S3C24X0_REG8 ALMDATE;
542 S3C24X0_REG8 res7[3];
543 S3C24X0_REG8 ALMMON;
544 S3C24X0_REG8 res8[3];
545 S3C24X0_REG8 ALMYEAR;
546 S3C24X0_REG8 res9[3];
547 S3C24X0_REG8 RTCRST;
548 S3C24X0_REG8 res10[3];
549 S3C24X0_REG8 BCDSEC;
550 S3C24X0_REG8 res11[3];
551 S3C24X0_REG8 BCDMIN;
552 S3C24X0_REG8 res12[3];
553 S3C24X0_REG8 BCDHOUR;
554 S3C24X0_REG8 res13[3];
555 S3C24X0_REG8 BCDDATE;
556 S3C24X0_REG8 res14[3];
557 S3C24X0_REG8 BCDDAY;
558 S3C24X0_REG8 res15[3];
559 S3C24X0_REG8 BCDMON;
560 S3C24X0_REG8 res16[3];
561 S3C24X0_REG8 BCDYEAR;
562 S3C24X0_REG8 res17[3];
563 #endif
564 } /*__attribute__((__packed__))*/ S3C24X0_RTC;
565
566
567 /* ADC (see manual chapter 16) */
568 typedef struct {
569 S3C24X0_REG32 ADCCON;
570 S3C24X0_REG32 ADCDAT;
571 } /*__attribute__((__packed__))*/ S3C2400_ADC;
572
573
574 /* ADC (see manual chapter 16) */
575 typedef struct {
576 S3C24X0_REG32 ADCCON;
577 S3C24X0_REG32 ADCTSC;
578 S3C24X0_REG32 ADCDLY;
579 S3C24X0_REG32 ADCDAT0;
580 S3C24X0_REG32 ADCDAT1;
581 } /*__attribute__((__packed__))*/ S3C2410_ADC;
582
583
584 /* SPI (see manual chapter 22) */
585 typedef struct {
586 S3C24X0_REG32 SPCON;
587 S3C24X0_REG32 SPSTA;
588 S3C24X0_REG32 SPPIN;
589 S3C24X0_REG32 SPPRE;
590 S3C24X0_REG32 SPTDAT;
591 S3C24X0_REG32 SPRDAT;
592 S3C24X0_REG32 res[2];
593 } __attribute__((__packed__)) S3C24X0_SPI_CHANNEL;
594
595 typedef struct {
596 S3C24X0_SPI_CHANNEL ch[S3C24X0_SPI_CHANNELS];
597 } /*__attribute__((__packed__))*/ S3C24X0_SPI;
598
599
600 /* MMC INTERFACE (see S3C2400 manual chapter 19) */
601 typedef struct {
602 #ifdef __BIG_ENDIAN
603 S3C24X0_REG8 res1[3];
604 S3C24X0_REG8 MMCON;
605 S3C24X0_REG8 res2[3];
606 S3C24X0_REG8 MMCRR;
607 S3C24X0_REG8 res3[3];
608 S3C24X0_REG8 MMFCON;
609 S3C24X0_REG8 res4[3];
610 S3C24X0_REG8 MMSTA;
611 S3C24X0_REG16 res5;
612 S3C24X0_REG16 MMFSTA;
613 S3C24X0_REG8 res6[3];
614 S3C24X0_REG8 MMPRE;
615 S3C24X0_REG16 res7;
616 S3C24X0_REG16 MMLEN;
617 S3C24X0_REG8 res8[3];
618 S3C24X0_REG8 MMCR7;
619 S3C24X0_REG32 MMRSP[4];
620 S3C24X0_REG8 res9[3];
621 S3C24X0_REG8 MMCMD0;
622 S3C24X0_REG32 MMCMD1;
623 S3C24X0_REG16 res10;
624 S3C24X0_REG16 MMCR16;
625 S3C24X0_REG8 res11[3];
626 S3C24X0_REG8 MMDAT;
627 #else
628 S3C24X0_REG8 MMCON;
629 S3C24X0_REG8 res1[3];
630 S3C24X0_REG8 MMCRR;
631 S3C24X0_REG8 res2[3];
632 S3C24X0_REG8 MMFCON;
633 S3C24X0_REG8 res3[3];
634 S3C24X0_REG8 MMSTA;
635 S3C24X0_REG8 res4[3];
636 S3C24X0_REG16 MMFSTA;
637 S3C24X0_REG16 res5;
638 S3C24X0_REG8 MMPRE;
639 S3C24X0_REG8 res6[3];
640 S3C24X0_REG16 MMLEN;
641 S3C24X0_REG16 res7;
642 S3C24X0_REG8 MMCR7;
643 S3C24X0_REG8 res8[3];
644 S3C24X0_REG32 MMRSP[4];
645 S3C24X0_REG8 MMCMD0;
646 S3C24X0_REG8 res9[3];
647 S3C24X0_REG32 MMCMD1;
648 S3C24X0_REG16 MMCR16;
649 S3C24X0_REG16 res10;
650 S3C24X0_REG8 MMDAT;
651 S3C24X0_REG8 res11[3];
652 #endif
653 } /*__attribute__((__packed__))*/ S3C2400_MMC;
654
655
656 /* SD INTERFACE (see S3C2410 manual chapter 19) */
657 typedef struct {
658 S3C24X0_REG32 SDICON;
659 S3C24X0_REG32 SDIPRE;
660 S3C24X0_REG32 SDICARG;
661 S3C24X0_REG32 SDICCON;
662 S3C24X0_REG32 SDICSTA;
663 S3C24X0_REG32 SDIRSP0;
664 S3C24X0_REG32 SDIRSP1;
665 S3C24X0_REG32 SDIRSP2;
666 S3C24X0_REG32 SDIRSP3;
667 S3C24X0_REG32 SDIDTIMER;
668 S3C24X0_REG32 SDIBSIZE;
669 S3C24X0_REG32 SDIDCON;
670 S3C24X0_REG32 SDIDCNT;
671 S3C24X0_REG32 SDIDSTA;
672 S3C24X0_REG32 SDIFSTA;
673 #ifdef __BIG_ENDIAN
674 S3C24X0_REG8 res[3];
675 S3C24X0_REG8 SDIDAT;
676 #else
677 S3C24X0_REG8 SDIDAT;
678 S3C24X0_REG8 res[3];
679 #endif
680 S3C24X0_REG32 SDIIMSK;
681 } /*__attribute__((__packed__))*/ S3C2410_SDI;
682
683
684 #if 0
685 /* Memory control */
686 #define rBWSCON (*(volatile unsigned *)0x48000000)
687 #define rBANKCON0 (*(volatile unsigned *)0x48000004)
688 #define rBANKCON1 (*(volatile unsigned *)0x48000008)
689 #define rBANKCON2 (*(volatile unsigned *)0x4800000C)
690 #define rBANKCON3 (*(volatile unsigned *)0x48000010)
691 #define rBANKCON4 (*(volatile unsigned *)0x48000014)
692 #define rBANKCON5 (*(volatile unsigned *)0x48000018)
693 #define rBANKCON6 (*(volatile unsigned *)0x4800001C)
694 #define rBANKCON7 (*(volatile unsigned *)0x48000020)
695 #define rREFRESH (*(volatile unsigned *)0x48000024)
696 #define rBANKSIZE (*(volatile unsigned *)0x48000028)
697 #define rMRSRB6 (*(volatile unsigned *)0x4800002C)
698 #define rMRSRB7 (*(volatile unsigned *)0x48000030)
699
700
701 /* USB HOST */
702 #define rHcRevision (*(volatile unsigned *)0x49000000)
703 #define rHcControl (*(volatile unsigned *)0x49000004)
704 #define rHcCommonStatus (*(volatile unsigned *)0x49000008)
705 #define rHcInterruptStatus (*(volatile unsigned *)0x4900000C)
706 #define rHcInterruptEnable (*(volatile unsigned *)0x49000010)
707 #define rHcInterruptDisable (*(volatile unsigned *)0x49000014)
708 #define rHcHCCA (*(volatile unsigned *)0x49000018)
709 #define rHcPeriodCuttendED (*(volatile unsigned *)0x4900001C)
710 #define rHcControlHeadED (*(volatile unsigned *)0x49000020)
711 #define rHcControlCurrentED (*(volatile unsigned *)0x49000024)
712 #define rHcBulkHeadED (*(volatile unsigned *)0x49000028)
713 #define rHcBuldCurrentED (*(volatile unsigned *)0x4900002C)
714 #define rHcDoneHead (*(volatile unsigned *)0x49000030)
715 #define rHcRmInterval (*(volatile unsigned *)0x49000034)
716 #define rHcFmRemaining (*(volatile unsigned *)0x49000038)
717 #define rHcFmNumber (*(volatile unsigned *)0x4900003C)
718 #define rHcPeriodicStart (*(volatile unsigned *)0x49000040)
719 #define rHcLSThreshold (*(volatile unsigned *)0x49000044)
720 #define rHcRhDescriptorA (*(volatile unsigned *)0x49000048)
721 #define rHcRhDescriptorB (*(volatile unsigned *)0x4900004C)
722 #define rHcRhStatus (*(volatile unsigned *)0x49000050)
723 #define rHcRhPortStatus1 (*(volatile unsigned *)0x49000054)
724 #define rHcRhPortStatus2 (*(volatile unsigned *)0x49000058)
725
726
727 /* INTERRUPT */
728 #define rSRCPND (*(volatile unsigned *)0x4A000000)
729 #define rINTMOD (*(volatile unsigned *)0x4A000004)
730 #define rINTMSK (*(volatile unsigned *)0x4A000008)
731 #define rPRIORITY (*(volatile unsigned *)0x4A00000C)
732 #define rINTPND (*(volatile unsigned *)0x4A000010)
733 #define rINTOFFSET (*(volatile unsigned *)0x4A000014)
734 #define rSUBSRCPND (*(volatile unsigned *)0x4A000018)
735 #define rINTSUBMSK (*(volatile unsigned *)0x4A00001C)
736
737
738 /* DMA */
739 #define rDISRC0 (*(volatile unsigned *)0x4B000000)
740 #define rDISRCC0 (*(volatile unsigned *)0x4B000004)
741 #define rDIDST0 (*(volatile unsigned *)0x4B000008)
742 #define rDIDSTC0 (*(volatile unsigned *)0x4B00000C)
743 #define rDCON0 (*(volatile unsigned *)0x4B000010)
744 #define rDSTAT0 (*(volatile unsigned *)0x4B000014)
745 #define rDCSRC0 (*(volatile unsigned *)0x4B000018)
746 #define rDCDST0 (*(volatile unsigned *)0x4B00001C)
747 #define rDMASKTRIG0 (*(volatile unsigned *)0x4B000020)
748 #define rDISRC1 (*(volatile unsigned *)0x4B000040)
749 #define rDISRCC1 (*(volatile unsigned *)0x4B000044)
750 #define rDIDST1 (*(volatile unsigned *)0x4B000048)
751 #define rDIDSTC1 (*(volatile unsigned *)0x4B00004C)
752 #define rDCON1 (*(volatile unsigned *)0x4B000050)
753 #define rDSTAT1 (*(volatile unsigned *)0x4B000054)
754 #define rDCSRC1 (*(volatile unsigned *)0x4B000058)
755 #define rDCDST1 (*(volatile unsigned *)0x4B00005C)
756 #define rDMASKTRIG1 (*(volatile unsigned *)0x4B000060)
757 #define rDISRC2 (*(volatile unsigned *)0x4B000080)
758 #define rDISRCC2 (*(volatile unsigned *)0x4B000084)
759 #define rDIDST2 (*(volatile unsigned *)0x4B000088)
760 #define rDIDSTC2 (*(volatile unsigned *)0x4B00008C)
761 #define rDCON2 (*(volatile unsigned *)0x4B000090)
762 #define rDSTAT2 (*(volatile unsigned *)0x4B000094)
763 #define rDCSRC2 (*(volatile unsigned *)0x4B000098)
764 #define rDCDST2 (*(volatile unsigned *)0x4B00009C)
765 #define rDMASKTRIG2 (*(volatile unsigned *)0x4B0000A0)
766 #define rDISRC3 (*(volatile unsigned *)0x4B0000C0)
767 #define rDISRCC3 (*(volatile unsigned *)0x4B0000C4)
768 #define rDIDST3 (*(volatile unsigned *)0x4B0000C8)
769 #define rDIDSTC3 (*(volatile unsigned *)0x4B0000CC)
770 #define rDCON3 (*(volatile unsigned *)0x4B0000D0)
771 #define rDSTAT3 (*(volatile unsigned *)0x4B0000D4)
772 #define rDCSRC3 (*(volatile unsigned *)0x4B0000D8)
773 #define rDCDST3 (*(volatile unsigned *)0x4B0000DC)
774 #define rDMASKTRIG3 (*(volatile unsigned *)0x4B0000E0)
775
776
777 /* CLOCK & POWER MANAGEMENT */
778 #define rLOCKTIME (*(volatile unsigned *)0x4C000000)
779 #define rMPLLCON (*(volatile unsigned *)0x4C000004)
780 #define rUPLLCON (*(volatile unsigned *)0x4C000008)
781 #define rCLKCON (*(volatile unsigned *)0x4C00000C)
782 #define rCLKSLOW (*(volatile unsigned *)0x4C000010)
783 #define rCLKDIVN (*(volatile unsigned *)0x4C000014)
784
785
786 /* LCD CONTROLLER */
787 #define rLCDCON1 (*(volatile unsigned *)0x4D000000)
788 #define rLCDCON2 (*(volatile unsigned *)0x4D000004)
789 #define rLCDCON3 (*(volatile unsigned *)0x4D000008)
790 #define rLCDCON4 (*(volatile unsigned *)0x4D00000C)
791 #define rLCDCON5 (*(volatile unsigned *)0x4D000010)
792 #define rLCDSADDR1 (*(volatile unsigned *)0x4D000014)
793 #define rLCDSADDR2 (*(volatile unsigned *)0x4D000018)
794 #define rLCDSADDR3 (*(volatile unsigned *)0x4D00001C)
795 #define rREDLUT (*(volatile unsigned *)0x4D000020)
796 #define rGREENLUT (*(volatile unsigned *)0x4D000024)
797 #define rBLUELUT (*(volatile unsigned *)0x4D000028)
798 #define rDITHMODE (*(volatile unsigned *)0x4D00004C)
799 #define rTPAL (*(volatile unsigned *)0x4D000050)
800 #define rLCDINTPND (*(volatile unsigned *)0x4D000054)
801 #define rLCDSRCPND (*(volatile unsigned *)0x4D000058)
802 #define rLCDINTMSK (*(volatile unsigned *)0x4D00005C)
803
804
805 /* NAND FLASH */
806 #define rNFCONF (*(volatile unsigned *)0x4E000000)
807 #define rNFCMD (*(volatile unsigned *)0x4E000004)
808 #define rNFADDR (*(volatile unsigned *)0x4E000008)
809 #define rNFDATA (*(volatile unsigned *)0x4E00000C)
810 #define rNFSTAT (*(volatile unsigned *)0x4E000010)
811 #define rNFECC (*(volatile unsigned *)0x4E000014)
812
813
814 /* UART */
815 #define rULCON0 (*(volatile unsigned *)0x50000000)
816 #define rUCON0 (*(volatile unsigned *)0x50000004)
817 #define rUFCON0 (*(volatile unsigned *)0x50000008)
818 #define rUMCON0 (*(volatile unsigned *)0x5000000C)
819 #define rUTRSTAT0 (*(volatile unsigned *)0x50000010)
820 #define rUERSTAT0 (*(volatile unsigned *)0x50000014)
821 #define rUFSTAT0 (*(volatile unsigned *)0x50000018)
822 #define rUMSTAT0 (*(volatile unsigned *)0x5000001C)
823 #define rUBRDIV0 (*(volatile unsigned *)0x50000028)
824
825 #define rULCON1 (*(volatile unsigned *)0x50004000)
826 #define rUCON1 (*(volatile unsigned *)0x50004004)
827 #define rUFCON1 (*(volatile unsigned *)0x50004008)
828 #define rUMCON1 (*(volatile unsigned *)0x5000400C)
829 #define rUTRSTAT1 (*(volatile unsigned *)0x50004010)
830 #define rUERSTAT1 (*(volatile unsigned *)0x50004014)
831 #define rUFSTAT1 (*(volatile unsigned *)0x50004018)
832 #define rUMSTAT1 (*(volatile unsigned *)0x5000401C)
833 #define rUBRDIV1 (*(volatile unsigned *)0x50004028)
834
835 #define rULCON2 (*(volatile unsigned *)0x50008000)
836 #define rUCON2 (*(volatile unsigned *)0x50008004)
837 #define rUFCON2 (*(volatile unsigned *)0x50008008)
838 #define rUTRSTAT2 (*(volatile unsigned *)0x50008010)
839 #define rUERSTAT2 (*(volatile unsigned *)0x50008014)
840 #define rUFSTAT2 (*(volatile unsigned *)0x50008018)
841 #define rUBRDIV2 (*(volatile unsigned *)0x50008028)
842
843 #ifdef __BIG_ENDIAN
844 #define rUTXH0 (*(volatile unsigned char *)0x50000023)
845 #define rURXH0 (*(volatile unsigned char *)0x50000027)
846 #define rUTXH1 (*(volatile unsigned char *)0x50004023)
847 #define rURXH1 (*(volatile unsigned char *)0x50004027)
848 #define rUTXH2 (*(volatile unsigned char *)0x50008023)
849 #define rURXH2 (*(volatile unsigned char *)0x50008027)
850
851 #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
852 #define RdURXH0() (*(volatile unsigned char *)0x50000027)
853 #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
854 #define RdURXH1() (*(volatile unsigned char *)0x50004027)
855 #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
856 #define RdURXH2() (*(volatile unsigned char *)0x50008027)
857
858 #define UTXH0 (0x50000020+3) /* byte_access address by DMA */
859 #define URXH0 (0x50000024+3)
860 #define UTXH1 (0x50004020+3)
861 #define URXH1 (0x50004024+3)
862 #define UTXH2 (0x50008020+3)
863 #define URXH2 (0x50008024+3)
864
865 #else /* Little Endian */
866 #define rUTXH0 (*(volatile unsigned char *)0x50000020)
867 #define rURXH0 (*(volatile unsigned char *)0x50000024)
868 #define rUTXH1 (*(volatile unsigned char *)0x50004020)
869 #define rURXH1 (*(volatile unsigned char *)0x50004024)
870 #define rUTXH2 (*(volatile unsigned char *)0x50008020)
871 #define rURXH2 (*(volatile unsigned char *)0x50008024)
872
873 #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
874 #define RdURXH0() (*(volatile unsigned char *)0x50000024)
875 #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
876 #define RdURXH1() (*(volatile unsigned char *)0x50004024)
877 #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
878 #define RdURXH2() (*(volatile unsigned char *)0x50008024)
879
880 #define UTXH0 (0x50000020) /* byte_access address by DMA */
881 #define URXH0 (0x50000024)
882 #define UTXH1 (0x50004020)
883 #define URXH1 (0x50004024)
884 #define UTXH2 (0x50008020)
885 #define URXH2 (0x50008024)
886 #endif
887
888
889 /* PWM TIMER */
890 #define rTCFG0 (*(volatile unsigned *)0x51000000)
891 #define rTCFG1 (*(volatile unsigned *)0x51000004)
892 #define rTCON (*(volatile unsigned *)0x51000008)
893 #define rTCNTB0 (*(volatile unsigned *)0x5100000C)
894 #define rTCMPB0 (*(volatile unsigned *)0x51000010)
895 #define rTCNTO0 (*(volatile unsigned *)0x51000014)
896 #define rTCNTB1 (*(volatile unsigned *)0x51000018)
897 #define rTCMPB1 (*(volatile unsigned *)0x5100001C)
898 #define rTCNTO1 (*(volatile unsigned *)0x51000020)
899 #define rTCNTB2 (*(volatile unsigned *)0x51000024)
900 #define rTCMPB2 (*(volatile unsigned *)0x51000028)
901 #define rTCNTO2 (*(volatile unsigned *)0x5100002C)
902 #define rTCNTB3 (*(volatile unsigned *)0x51000030)
903 #define rTCMPB3 (*(volatile unsigned *)0x51000034)
904 #define rTCNTO3 (*(volatile unsigned *)0x51000038)
905 #define rTCNTB4 (*(volatile unsigned *)0x5100003C)
906 #define rTCNTO4 (*(volatile unsigned *)0x51000040)
907
908
909 /* USB DEVICE */
910 #ifdef __BIG_ENDIAN
911 #define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143)
912 #define rPWR_REG (*(volatile unsigned char *)0x52000147)
913 #define rEP_INT_REG (*(volatile unsigned char *)0x5200014B)
914 #define rUSB_INT_REG (*(volatile unsigned char *)0x5200015B)
915 #define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015F)
916 #define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016F)
917 #define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173)
918 #define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177)
919 #define rINDEX_REG (*(volatile unsigned char *)0x5200017B)
920 #define rMAXP_REG (*(volatile unsigned char *)0x52000183)
921 #define rEP0_CSR (*(volatile unsigned char *)0x52000187)
922 #define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187)
923 #define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018B)
924 #define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193)
925 #define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
926 #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019B)
927 #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019F)
928 #define rEP0_FIFO (*(volatile unsigned char *)0x520001C3)
929 #define rEP1_FIFO (*(volatile unsigned char *)0x520001C7)
930 #define rEP2_FIFO (*(volatile unsigned char *)0x520001CB)
931 #define rEP3_FIFO (*(volatile unsigned char *)0x520001CF)
932 #define rEP4_FIFO (*(volatile unsigned char *)0x520001D3)
933 #define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203)
934 #define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207)
935 #define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020B)
936 #define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020F)
937 #define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000213)
938 #define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000217)
939 #define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021B)
940 #define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021F)
941 #define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223)
942 #define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000227)
943 #define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x5200022B)
944 #define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022F)
945 #define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243)
946 #define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247)
947 #define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024B)
948 #define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024F)
949 #define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000253)
950 #define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000257)
951 #define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025B)
952 #define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025F)
953 #define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263)
954 #define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000267)
955 #define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x5200026B)
956 #define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026F)
957 #else /* little endian */
958 #define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140)
959 #define rPWR_REG (*(volatile unsigned char *)0x52000144)
960 #define rEP_INT_REG (*(volatile unsigned char *)0x52000148)
961 #define rUSB_INT_REG (*(volatile unsigned char *)0x52000158)
962 #define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015C)
963 #define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016C)
964 #define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170)
965 #define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174)
966 #define rINDEX_REG (*(volatile unsigned char *)0x52000178)
967 #define rMAXP_REG (*(volatile unsigned char *)0x52000180)
968 #define rEP0_CSR (*(volatile unsigned char *)0x52000184)
969 #define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184)
970 #define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188)
971 #define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190)
972 #define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
973 #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198)
974 #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019C)
975 #define rEP0_FIFO (*(volatile unsigned char *)0x520001C0)
976 #define rEP1_FIFO (*(volatile unsigned char *)0x520001C4)
977 #define rEP2_FIFO (*(volatile unsigned char *)0x520001C8)
978 #define rEP3_FIFO (*(volatile unsigned char *)0x520001CC)
979 #define rEP4_FIFO (*(volatile unsigned char *)0x520001D0)
980 #define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200)
981 #define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204)
982 #define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208)
983 #define rEP1_DMA_TX_LO (*(volatile unsigned char *)0x5200020C)
984 #define rEP1_DMA_TX_MD (*(volatile unsigned char *)0x52000210)
985 #define rEP1_DMA_TX_HI (*(volatile unsigned char *)0x52000214)
986 #define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218)
987 #define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021C)
988 #define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220)
989 #define rEP2_DMA_TX_LO (*(volatile unsigned char *)0x52000224)
990 #define rEP2_DMA_TX_MD (*(volatile unsigned char *)0x52000228)
991 #define rEP2_DMA_TX_HI (*(volatile unsigned char *)0x5200022C)
992 #define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240)
993 #define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244)
994 #define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248)
995 #define rEP3_DMA_TX_LO (*(volatile unsigned char *)0x5200024C)
996 #define rEP3_DMA_TX_MD (*(volatile unsigned char *)0x52000250)
997 #define rEP3_DMA_TX_HI (*(volatile unsigned char *)0x52000254)
998 #define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258)
999 #define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025C)
1000 #define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260)
1001 #define rEP4_DMA_TX_LO (*(volatile unsigned char *)0x52000264)
1002 #define rEP4_DMA_TX_MD (*(volatile unsigned char *)0x52000268)
1003 #define rEP4_DMA_TX_HI (*(volatile unsigned char *)0x5200026C)
1004 #endif /* __BIG_ENDIAN */
1005
1006
1007 /* WATCH DOG TIMER */
1008 #define rWTCON (*(volatile unsigned *)0x53000000)
1009 #define rWTDAT (*(volatile unsigned *)0x53000004)
1010 #define rWTCNT (*(volatile unsigned *)0x53000008)
1011
1012
1013 /* IIC */
1014 #define rIICCON (*(volatile unsigned *)0x54000000)
1015 #define rIICSTAT (*(volatile unsigned *)0x54000004)
1016 #define rIICADD (*(volatile unsigned *)0x54000008)
1017 #define rIICDS (*(volatile unsigned *)0x5400000C)
1018
1019
1020 /* IIS */
1021 #define rIISCON (*(volatile unsigned *)0x55000000)
1022 #define rIISMOD (*(volatile unsigned *)0x55000004)
1023 #define rIISPSR (*(volatile unsigned *)0x55000008)
1024 #define rIISFCON (*(volatile unsigned *)0x5500000C)
1025
1026 #ifdef __BIG_ENDIAN
1027 #define IISFIF ((volatile unsigned short *)0x55000012)
1028 #else /* little endian */
1029 #define IISFIF ((volatile unsigned short *)0x55000010)
1030 #endif
1031
1032
1033 /* I/O PORT */
1034 #define rGPACON (*(volatile unsigned *)0x56000000)
1035 #define rGPADAT (*(volatile unsigned *)0x56000004)
1036
1037 #define rGPBCON (*(volatile unsigned *)0x56000010)
1038 #define rGPBDAT (*(volatile unsigned *)0x56000014)
1039 #define rGPBUP (*(volatile unsigned *)0x56000018)
1040
1041 #define rGPCCON (*(volatile unsigned *)0x56000020)
1042 #define rGPCDAT (*(volatile unsigned *)0x56000024)
1043 #define rGPCUP (*(volatile unsigned *)0x56000028)
1044
1045 #define rGPDCON (*(volatile unsigned *)0x56000030)
1046 #define rGPDDAT (*(volatile unsigned *)0x56000034)
1047 #define rGPDUP (*(volatile unsigned *)0x56000038)
1048
1049 #define rGPECON (*(volatile unsigned *)0x56000040)
1050 #define rGPEDAT (*(volatile unsigned *)0x56000044)
1051 #define rGPEUP (*(volatile unsigned *)0x56000048)
1052
1053 #define rGPFCON (*(volatile unsigned *)0x56000050)
1054 #define rGPFDAT (*(volatile unsigned *)0x56000054)
1055 #define rGPFUP (*(volatile unsigned *)0x56000058)
1056
1057 #define rGPGCON (*(volatile unsigned *)0x56000060)
1058 #define rGPGDAT (*(volatile unsigned *)0x56000064)
1059 #define rGPGUP (*(volatile unsigned *)0x56000068)
1060
1061 #define rGPHCON (*(volatile unsigned *)0x56000070)
1062 #define rGPHDAT (*(volatile unsigned *)0x56000074)
1063 #define rGPHUP (*(volatile unsigned *)0x56000078)
1064
1065 #define rMISCCR (*(volatile unsigned *)0x56000080)
1066 #define rDCLKCON (*(volatile unsigned *)0x56000084)
1067 #define rEXTINT0 (*(volatile unsigned *)0x56000088)
1068 #define rEXTINT1 (*(volatile unsigned *)0x5600008C)
1069 #define rEXTINT2 (*(volatile unsigned *)0x56000090)
1070 #define rEINTFLT0 (*(volatile unsigned *)0x56000094)
1071 #define rEINTFLT1 (*(volatile unsigned *)0x56000098)
1072 #define rEINTFLT2 (*(volatile unsigned *)0x5600009C)
1073 #define rEINTFLT3 (*(volatile unsigned *)0x560000A0)
1074 #define rEINTMASK (*(volatile unsigned *)0x560000A4)
1075 #define rEINTPEND (*(volatile unsigned *)0x560000A8)
1076 #define rGSTATUS0 (*(volatile unsigned *)0x560000AC)
1077 #define rGSTATUS1 (*(volatile unsigned *)0x560000B0)
1078
1079
1080 /* RTC */
1081 #ifdef __BIG_ENDIAN
1082 #define rRTCCON (*(volatile unsigned char *)0x57000043)
1083 #define rTICNT (*(volatile unsigned char *)0x57000047)
1084 #define rRTCALM (*(volatile unsigned char *)0x57000053)
1085 #define rALMSEC (*(volatile unsigned char *)0x57000057)
1086 #define rALMMIN (*(volatile unsigned char *)0x5700005B)
1087 #define rALMHOUR (*(volatile unsigned char *)0x5700005F)
1088 #define rALMDATE (*(volatile unsigned char *)0x57000063)
1089 #define rALMMON (*(volatile unsigned char *)0x57000067)
1090 #define rALMYEAR (*(volatile unsigned char *)0x5700006B)
1091 #define rRTCRST (*(volatile unsigned char *)0x5700006F)
1092 #define rBCDSEC (*(volatile unsigned char *)0x57000073)
1093 #define rBCDMIN (*(volatile unsigned char *)0x57000077)
1094 #define rBCDHOUR (*(volatile unsigned char *)0x5700007B)
1095 #define rBCDDATE (*(volatile unsigned char *)0x5700007F)
1096 #define rBCDDAY (*(volatile unsigned char *)0x57000083)
1097 #define rBCDMON (*(volatile unsigned char *)0x57000087)
1098 #define rBCDYEAR (*(volatile unsigned char *)0x5700008B)
1099 #else /* little endian */
1100 #define rRTCCON (*(volatile unsigned char *)0x57000040)
1101 #define rTICNT (*(volatile unsigned char *)0x57000044)
1102 #define rRTCALM (*(volatile unsigned char *)0x57000050)
1103 #define rALMSEC (*(volatile unsigned char *)0x57000054)
1104 #define rALMMIN (*(volatile unsigned char *)0x57000058)
1105 #define rALMHOUR (*(volatile unsigned char *)0x5700005C)
1106 #define rALMDATE (*(volatile unsigned char *)0x57000060)
1107 #define rALMMON (*(volatile unsigned char *)0x57000064)
1108 #define rALMYEAR (*(volatile unsigned char *)0x57000068)
1109 #define rRTCRST (*(volatile unsigned char *)0x5700006C)
1110 #define rBCDSEC (*(volatile unsigned char *)0x57000070)
1111 #define rBCDMIN (*(volatile unsigned char *)0x57000074)
1112 #define rBCDHOUR (*(volatile unsigned char *)0x57000078)
1113 #define rBCDDATE (*(volatile unsigned char *)0x5700007C)
1114 #define rBCDDAY (*(volatile unsigned char *)0x57000080)
1115 #define rBCDMON (*(volatile unsigned char *)0x57000084)
1116 #define rBCDYEAR (*(volatile unsigned char *)0x57000088)
1117 #endif
1118
1119
1120 /* ADC */
1121 #define rADCCON (*(volatile unsigned *)0x58000000)
1122 #define rADCTSC (*(volatile unsigned *)0x58000004)
1123 #define rADCDLY (*(volatile unsigned *)0x58000008)
1124 #define rADCDAT0 (*(volatile unsigned *)0x5800000C)
1125 #define rADCDAT1 (*(volatile unsigned *)0x58000010)
1126
1127
1128 /* SPI */
1129 #define rSPCON0 (*(volatile unsigned *)0x59000000)
1130 #define rSPSTA0 (*(volatile unsigned *)0x59000004)
1131 #define rSPPIN0 (*(volatile unsigned *)0x59000008)
1132 #define rSPPRE0 (*(volatile unsigned *)0x5900000C)
1133 #define rSPTDAT0 (*(volatile unsigned *)0x59000010)
1134 #define rSPRDAT0 (*(volatile unsigned *)0x59000014)
1135 #define rSPCON1 (*(volatile unsigned *)0x59000020)
1136 #define rSPSTA1 (*(volatile unsigned *)0x59000024)
1137 #define rSPPIN1 (*(volatile unsigned *)0x59000028)
1138 #define rSPPRE1 (*(volatile unsigned *)0x5900002C)
1139 #define rSPTDAT1 (*(volatile unsigned *)0x59000030)
1140 #define rSPRDAT1 (*(volatile unsigned *)0x59000034)
1141
1142
1143 /* SD INTERFACE */
1144 #define rSDICON (*(volatile unsigned *)0x5A000000)
1145 #define rSDIPRE (*(volatile unsigned *)0x5A000004)
1146 #define rSDICmdArg (*(volatile unsigned *)0x5A000008)
1147 #define rSDICmdCon (*(volatile unsigned *)0x5A00000C)
1148 #define rSDICmdSta (*(volatile unsigned *)0x5A000010)
1149 #define rSDIRSP0 (*(volatile unsigned *)0x5A000014)
1150 #define rSDIRSP1 (*(volatile unsigned *)0x5A000018)
1151 #define rSDIRSP2 (*(volatile unsigned *)0x5A00001C)
1152 #define rSDIRSP3 (*(volatile unsigned *)0x5A000020)
1153 #define rSDIDTimer (*(volatile unsigned *)0x5A000024)
1154 #define rSDIBSize (*(volatile unsigned *)0x5A000028)
1155 #define rSDIDatCon (*(volatile unsigned *)0x5A00002C)
1156 #define rSDIDatCnt (*(volatile unsigned *)0x5A000030)
1157 #define rSDIDatSta (*(volatile unsigned *)0x5A000034)
1158 #define rSDIFSTA (*(volatile unsigned *)0x5A000038)
1159 #ifdef __BIG_ENDIAN
1160 #define rSDIDAT (*(volatile unsigned char *)0x5A00003F)
1161 #else
1162 #define rSDIDAT (*(volatile unsigned char *)0x5A00003C)
1163 #endif
1164 #define rSDIIntMsk (*(volatile unsigned *)0x5A000040)
1165
1166 #endif
1167
1168 #endif /*__S3C24X0_H__*/
/////////////
include/s3c2440.h 为新引入的文件，内容如下，尾部少许修改：（来自2440test）
1 //=============================================================================
2 // File Name : 2440addr.h
3 // Function : S3C2440 Define Address Register
4 // History
5 // 0.0 : Programming start (February 15,2002) -> SOP
6 // Revision : 03.11.2003 ver 0.0 Attatched for 2440
7 //=============================================================================
8
9 #ifndef __2440ADDR_H__
10 #define __2440ADDR_H__
11
12 #ifdef __cplusplus
13 extern "C" {
14 #endif
15
16 #include "option.h"
17
18
19 // Memory control
20 #define rBWSCON (*(volatile unsigned *)0x48000000) //Bus width & wait status
21 #define rBANKCON0 (*(volatile unsigned *)0x48000004) //Boot ROM control
22 #define rBANKCON1 (*(volatile unsigned *)0x48000008) //BANK1 control
23 #define rBANKCON2 (*(volatile unsigned *)0x4800000c) //BANK2 cControl
24 #define rBANKCON3 (*(volatile unsigned *)0x48000010) //BANK3 control
25 #define rBANKCON4 (*(volatile unsigned *)0x48000014) //BANK4 control
26 #define rBANKCON5 (*(volatile unsigned *)0x48000018) //BANK5 control
27 #define rBANKCON6 (*(volatile unsigned *)0x4800001c) //BANK6 control
28 #define rBANKCON7 (*(volatile unsigned *)0x48000020) //BANK7 control
29 #define rREFRESH (*(volatile unsigned *)0x48000024) //DRAM/SDRAM refresh
30 #define rBANKSIZE (*(volatile unsigned *)0x48000028) //Flexible Bank Size
31 #define rMRSRB6 (*(volatile unsigned *)0x4800002c) //Mode register set for SDRAM
32 #define rMRSRB7 (*(volatile unsigned *)0x48000030) //Mode register set for SDRAM
33
34
35 // USB Host
36
37
38 // INTERRUPT
39 #define rSRCPND (*(volatile unsigned *)0x4a000000) //Interrupt request status
40 #define rINTMOD (*(volatile unsigned *)0x4a000004) //Interrupt mode control
41 #define rINTMSK (*(volatile unsigned *)0x4a000008) //Interrupt mask control
42 #define rPRIORITY (*(volatile unsigned *)0x4a00000c) //IRQ priority control
43 #define rINTPND (*(volatile unsigned *)0x4a000010) //Interrupt request status
44 #define rINTOFFSET (*(volatile unsigned *)0x4a000014) //Interruot request source offset
45 #define rSUBSRCPND (*(volatile unsigned *)0x4a000018) //Sub source pending
46 #define rINTSUBMSK (*(volatile unsigned *)0x4a00001c) //Interrupt sub mask
47
48
49 // DMA
50 #define rDISRC0 (*(volatile unsigned *)0x4b000000) //DMA 0 Initial source
51 #define rDISRCC0 (*(volatile unsigned *)0x4b000004) //DMA 0 Initial source control
52 #define rDIDST0 (*(volatile unsigned *)0x4b000008) //DMA 0 Initial Destination
53 #define rDIDSTC0 (*(volatile unsigned *)0x4b00000c) //DMA 0 Initial Destination control
54 #define rDCON0 (*(volatile unsigned *)0x4b000010) //DMA 0 Control
55 #define rDSTAT0 (*(volatile unsigned *)0x4b000014) //DMA 0 Status
56 #define rDCSRC0 (*(volatile unsigned *)0x4b000018) //DMA 0 Current source
57 #define rDCDST0 (*(volatile unsigned *)0x4b00001c) //DMA 0 Current destination
58 #define rDMASKTRIG0 (*(volatile unsigned *)0x4b000020) //DMA 0 Mask trigger
59
60 #define rDISRC1 (*(volatile unsigned *)0x4b000040) //DMA 1 Initial source
61 #define rDISRCC1 (*(volatile unsigned *)0x4b000044) //DMA 1 Initial source control
62 #define rDIDST1 (*(volatile unsigned *)0x4b000048) //DMA 1 Initial Destination
63 #define rDIDSTC1 (*(volatile unsigned *)0x4b00004c) //DMA 1 Initial Destination control
64 #define rDCON1 (*(volatile unsigned *)0x4b000050) //DMA 1 Control
65 #define rDSTAT1 (*(volatile unsigned *)0x4b000054) //DMA 1 Status
66 #define rDCSRC1 (*(volatile unsigned *)0x4b000058) //DMA 1 Current source
67 #define rDCDST1 (*(volatile unsigned *)0x4b00005c) //DMA 1 Current destination
68 #define rDMASKTRIG1 (*(volatile unsigned *)0x4b000060) //DMA 1 Mask trigger
69
70 #define rDISRC2 (*(volatile unsigned *)0x4b000080) //DMA 2 Initial source
71 #define rDISRCC2 (*(volatile unsigned *)0x4b000084) //DMA 2 Initial source control
72 #define rDIDST2 (*(volatile unsigned *)0x4b000088) //DMA 2 Initial Destination
73 #define rDIDSTC2 (*(volatile unsigned *)0x4b00008c) //DMA 2 Initial Destination control
74 #define rDCON2 (*(volatile unsigned *)0x4b000090) //DMA 2 Control
75 #define rDSTAT2 (*(volatile unsigned *)0x4b000094) //DMA 2 Status
76 #define rDCSRC2 (*(volatile unsigned *)0x4b000098) //DMA 2 Current source
77 #define rDCDST2 (*(volatile unsigned *)0x4b00009c) //DMA 2 Current destination
78 #define rDMASKTRIG2 (*(volatile unsigned *)0x4b0000a0) //DMA 2 Mask trigger
79
80 #define rDISRC3 (*(volatile unsigned *)0x4b0000c0) //DMA 3 Initial source
81 #define rDISRCC3 (*(volatile unsigned *)0x4b0000c4) //DMA 3 Initial source control
82 #define rDIDST3 (*(volatile unsigned *)0x4b0000c8) //DMA 3 Initial Destination
83 #define rDIDSTC3 (*(volatile unsigned *)0x4b0000cc) //DMA 3 Initial Destination control
84 #define rDCON3 (*(volatile unsigned *)0x4b0000d0) //DMA 3 Control
85 #define rDSTAT3 (*(volatile unsigned *)0x4b0000d4) //DMA 3 Status
86 #define rDCSRC3 (*(volatile unsigned *)0x4b0000d8) //DMA 3 Current source
87 #define rDCDST3 (*(volatile unsigned *)0x4b0000dc) //DMA 3 Current destination
88 #define rDMASKTRIG3 (*(volatile unsigned *)0x4b0000e0) //DMA 3 Mask trigger
89
90
91 // CLOCK & POWER MANAGEMENT
92 #define rLOCKTIME (*(volatile unsigned *)0x4c000000) //PLL lock time counter
93 #define rMPLLCON (*(volatile unsigned *)0x4c000004) //MPLL Control
94 #define rUPLLCON (*(volatile unsigned *)0x4c000008) //UPLL Control
95 #define rCLKCON (*(volatile unsigned *)0x4c00000c) //Clock generator control
96 #define rCLKSLOW (*(volatile unsigned *)0x4c000010) //Slow clock control
97 #define rCLKDIVN (*(volatile unsigned *)0x4c000014) //Clock divider control
98 #define rCAMDIVN (*(volatile unsigned *)0x4c000018) //USB, CAM Clock divider control
99
100
101 // LCD CONTROLLER
102 #define rLCDCON1 (*(volatile unsigned *)0x4d000000) //LCD control 1
103 #define rLCDCON2 (*(volatile unsigned *)0x4d000004) //LCD control 2
104 #define rLCDCON3 (*(volatile unsigned *)0x4d000008) //LCD control 3
105 #define rLCDCON4 (*(volatile unsigned *)0x4d00000c) //LCD control 4
106 #define rLCDCON5 (*(volatile unsigned *)0x4d000010) //LCD control 5
107 #define rLCDSADDR1 (*(volatile unsigned *)0x4d000014) //STN/TFT Frame buffer start address 1
108 #define rLCDSADDR2 (*(volatile unsigned *)0x4d000018) //STN/TFT Frame buffer start address 2
109 #define rLCDSADDR3 (*(volatile unsigned *)0x4d00001c) //STN/TFT Virtual screen address set
110 #define rREDLUT (*(volatile unsigned *)0x4d000020) //STN Red lookup table
111 #define rGREENLUT (*(volatile unsigned *)0x4d000024) //STN Green lookup table
112 #define rBLUELUT (*(volatile unsigned *)0x4d000028) //STN Blue lookup table
113 #define rDITHMODE (*(volatile unsigned *)0x4d00004c) //STN Dithering mode
114 #define rTPAL (*(volatile unsigned *)0x4d000050) //TFT Temporary palette
115 #define rLCDINTPND (*(volatile unsigned *)0x4d000054) //LCD Interrupt pending
116 #define rLCDSRCPND (*(volatile unsigned *)0x4d000058) //LCD Interrupt source
117 #define rLCDINTMSK (*(volatile unsigned *)0x4d00005c) //LCD Interrupt mask
118 #define rTCONSEL (*(volatile unsigned *)0x4d000060) //LPC3600 Control --- edited by junon
119 #define PALETTE 0x4d000400 //Palette start address
120
121
122 //Nand Flash
123 #define rNFCONF (*(volatile unsigned *)0x4E000000) //NAND Flash configuration
124 #define rNFCONT (*(volatile unsigned *)0x4E000004) //NAND Flash control
125 #define rNFCMD (*(volatile unsigned *)0x4E000008) //NAND Flash command
126 #define rNFADDR (*(volatile unsigned *)0x4E00000C) //NAND Flash address
127 #define rNFDATA (*(volatile unsigned *)0x4E000010) //NAND Flash data
128 #define rNFDATA8 (*(volatile unsigned char *)0x4E000010) //NAND Flash data
129 #define NFDATA (0x4E000010) //NAND Flash data address
130 #define rNFMECCD0 (*(volatile unsigned *)0x4E000014) //NAND Flash ECC for Main Area
131 #define rNFMECCD1 (*(volatile unsigned *)0x4E000018)
132 #define rNFSECCD (*(volatile unsigned *)0x4E00001C) //NAND Flash ECC for Spare Area
133 #define rNFSTAT (*(volatile unsigned *)0x4E000020) //NAND Flash operation status
134 #define rNFESTAT0 (*(volatile unsigned *)0x4E000024)
135 #define rNFESTAT1 (*(volatile unsigned *)0x4E000028)
136 #define rNFMECC0 (*(volatile unsigned *)0x4E00002C)
137 #define rNFMECC1 (*(volatile unsigned *)0x4E000030)
138 #define rNFSECC (*(volatile unsigned *)0x4E000034)
139 #define rNFSBLK (*(volatile unsigned *)0x4E000038) //NAND Flash Start block address
140 #define rNFEBLK (*(volatile unsigned *)0x4E00003C) //NAND Flash End block address
141
142
143 //Camera Interface. Edited for 2440A
144 #define rCISRCFMT (*(volatile unsigned *)0x4F000000)
145 #define rCIWDOFST (*(volatile unsigned *)0x4F000004)
146 #define rCIGCTRL (*(volatile unsigned *)0x4F000008)
147 #define rCICOYSA1 (*(volatile unsigned *)0x4F000018)
148 #define rCICOYSA2 (*(volatile unsigned *)0x4F00001C)
149 #define rCICOYSA3 (*(volatile unsigned *)0x4F000020)
150 #define rCICOYSA4 (*(volatile unsigned *)0x4F000024)
151 #define rCICOCBSA1 (*(volatile unsigned *)0x4F000028)
152 #define rCICOCBSA2 (*(volatile unsigned *)0x4F00002C)
153 #define rCICOCBSA3 (*(volatile unsigned *)0x4F000030)
154 #define rCICOCBSA4 (*(volatile unsigned *)0x4F000034)
155 #define rCICOCRSA1 (*(volatile unsigned *)0x4F000038)
156 #define rCICOCRSA2 (*(volatile unsigned *)0x4F00003C)
157 #define rCICOCRSA3 (*(volatile unsigned *)0x4F000040)
158 #define rCICOCRSA4 (*(volatile unsigned *)0x4F000044)
159 #define rCICOTRGFMT (*(volatile unsigned *)0x4F000048)
160 #define rCICOCTRL (*(volatile unsigned *)0x4F00004C)
161 #define rCICOSCPRERATIO (*(volatile unsigned *)0x4F000050)
162 #define rCICOSCPREDST (*(volatile unsigned *)0x4F000054)
163 #define rCICOSCCTRL (*(volatile unsigned *)0x4F000058)
164 #define rCICOTAREA (*(volatile unsigned *)0x4F00005C)
165 #define rCICOSTATUS (*(volatile unsigned *)0x4F000064)
166 #define rCIPRCLRSA1 (*(volatile unsigned *)0x4F00006C)
167 #define rCIPRCLRSA2 (*(volatile unsigned *)0x4F000070)
168 #define rCIPRCLRSA3 (*(volatile unsigned *)0x4F000074)
169 #define rCIPRCLRSA4 (*(volatile unsigned *)0x4F000078)
170 #define rCIPRTRGFMT (*(volatile unsigned *)0x4F00007C)
171 #define rCIPRCTRL (*(volatile unsigned *)0x4F000080)
172 #define rCIPRSCPRERATIO (*(volatile unsigned *)0x4F000084)
173 #define rCIPRSCPREDST (*(volatile unsigned *)0x4F000088)
174 #define rCIPRSCCTRL (*(volatile unsigned *)0x4F00008C)
175 #define rCIPRTAREA (*(volatile unsigned *)0x4F000090)
176 #define rCIPRSTATUS (*(volatile unsigned *)0x4F000098)
177 #define rCIIMGCPT (*(volatile unsigned *)0x4F0000A0)
178
179
180 // UART
181 #define rULCON0 (*(volatile unsigned *)0x50000000) //UART 0 Line control
182 #define rUCON0 (*(volatile unsigned *)0x50000004) //UART 0 Control
183 #define rUFCON0 (*(volatile unsigned *)0x50000008) //UART 0 FIFO control
184 #define rUMCON0 (*(volatile unsigned *)0x5000000c) //UART 0 Modem control
185 #define rUTRSTAT0 (*(volatile unsigned *)0x50000010) //UART 0 Tx/Rx status
186 #define rUERSTAT0 (*(volatile unsigned *)0x50000014) //UART 0 Rx error status
187 #define rUFSTAT0 (*(volatile unsigned *)0x50000018) //UART 0 FIFO status
188 #define rUMSTAT0 (*(volatile unsigned *)0x5000001c) //UART 0 Modem status
189 #define rUBRDIV0 (*(volatile unsigned *)0x50000028) //UART 0 Baud rate divisor
190
191 #define rULCON1 (*(volatile unsigned *)0x50004000) //UART 1 Line control
192 #define rUCON1 (*(volatile unsigned *)0x50004004) //UART 1 Control
193 #define rUFCON1 (*(volatile unsigned *)0x50004008) //UART 1 FIFO control
194 #define rUMCON1 (*(volatile unsigned *)0x5000400c) //UART 1 Modem control
195 #define rUTRSTAT1 (*(volatile unsigned *)0x50004010) //UART 1 Tx/Rx status
196 #define rUERSTAT1 (*(volatile unsigned *)0x50004014) //UART 1 Rx error status
197 #define rUFSTAT1 (*(volatile unsigned *)0x50004018) //UART 1 FIFO status
198 #define rUMSTAT1 (*(volatile unsigned *)0x5000401c) //UART 1 Modem status
199 #define rUBRDIV1 (*(volatile unsigned *)0x50004028) //UART 1 Baud rate divisor
200 #define rULCON2 (*(volatile unsigned *)0x50008000) //UART 2 Line control
201 #define rUCON2 (*(volatile unsigned *)0x50008004) //UART 2 Control
202 #define rUFCON2 (*(volatile unsigned *)0x50008008) //UART 2 FIFO control
203 #define rUMCON2 (*(volatile unsigned *)0x5000800c) //UART 2 Modem control
204 #define rUTRSTAT2 (*(volatile unsigned *)0x50008010) //UART 2 Tx/Rx status
205 #define rUERSTAT2 (*(volatile unsigned *)0x50008014) //UART 2 Rx error status
206 #define rUFSTAT2 (*(volatile unsigned *)0x50008018) //UART 2 FIFO status
207 #define rUMSTAT2 (*(volatile unsigned *)0x5000801c) //UART 2 Modem status
208 #define rUBRDIV2 (*(volatile unsigned *)0x50008028) //UART 2 Baud rate divisor
209
210 #ifdef __BIG_ENDIAN
211 #define rUTXH0 (*(volatile unsigned char *)0x50000023) //UART 0 Transmission Hold
212 #define rURXH0 (*(volatile unsigned char *)0x50000027) //UART 0 Receive buffer
213 #define rUTXH1 (*(volatile unsigned char *)0x50004023) //UART 1 Transmission Hold
214 #define rURXH1 (*(volatile unsigned char *)0x50004027) //UART 1 Receive buffer
215 #define rUTXH2 (*(volatile unsigned char *)0x50008023) //UART 2 Transmission Hold
216 #define rURXH2 (*(volatile unsigned char *)0x50008027) //UART 2 Receive buffer
217
218 #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000023)=(unsigned char)(ch)
219 #define RdURXH0() (*(volatile unsigned char *)0x50000027)
220 #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004023)=(unsigned char)(ch)
221 #define RdURXH1() (*(volatile unsigned char *)0x50004027)
222 #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008023)=(unsigned char)(ch)
223 #define RdURXH2() (*(volatile unsigned char *)0x50008027)
224
225 #define UTXH0 (0x50000020+3) //Byte_access address by DMA
226 #define URXH0 (0x50000024+3)
227 #define UTXH1 (0x50004020+3)
228 #define URXH1 (0x50004024+3)
229 #define UTXH2 (0x50008020+3)
230 #define URXH2 (0x50008024+3)
231
232 #else //Little Endian
233 #define rUTXH0 (*(volatile unsigned char *)0x50000020) //UART 0 Transmission Hold
234 #define rURXH0 (*(volatile unsigned char *)0x50000024) //UART 0 Receive buffer
235 #define rUTXH1 (*(volatile unsigned char *)0x50004020) //UART 1 Transmission Hold
236 #define rURXH1 (*(volatile unsigned char *)0x50004024) //UART 1 Receive buffer
237 #define rUTXH2 (*(volatile unsigned char *)0x50008020) //UART 2 Transmission Hold
238 #define rURXH2 (*(volatile unsigned char *)0x50008024) //UART 2 Receive buffer
239
240 #define WrUTXH0(ch) (*(volatile unsigned char *)0x50000020)=(unsigned char)(ch)
241 #define RdURXH0() (*(volatile unsigned char *)0x50000024)
242 #define WrUTXH1(ch) (*(volatile unsigned char *)0x50004020)=(unsigned char)(ch)
243 #define RdURXH1() (*(volatile unsigned char *)0x50004024)
244 #define WrUTXH2(ch) (*(volatile unsigned char *)0x50008020)=(unsigned char)(ch)
245 #define RdURXH2() (*(volatile unsigned char *)0x50008024)
246
247 #define UTXH0 (0x50000020) //Byte_access address by DMA
248 #define URXH0 (0x50000024)
249 #define UTXH1 (0x50004020)
250 #define URXH1 (0x50004024)
251 #define UTXH2 (0x50008020)
252 #define URXH2 (0x50008024)
253 #endif
254
255
256 // PWM TIMER
257 #define rTCFG0 (*(volatile unsigned *)0x51000000) //Timer 0 configuration
258 #define rTCFG1 (*(volatile unsigned *)0x51000004) //Timer 1 configuration
259 #define rTCON (*(volatile unsigned *)0x51000008) //Timer control
260 #define rTCNTB0 (*(volatile unsigned *)0x5100000c) //Timer count buffer 0
261 #define rTCMPB0 (*(volatile unsigned *)0x51000010) //Timer compare buffer 0
262 #define rTCNTO0 (*(volatile unsigned *)0x51000014) //Timer count observation 0
263 #define rTCNTB1 (*(volatile unsigned *)0x51000018) //Timer count buffer 1
264 #define rTCMPB1 (*(volatile unsigned *)0x5100001c) //Timer compare buffer 1
265 #define rTCNTO1 (*(volatile unsigned *)0x51000020) //Timer count observation 1
266 #define rTCNTB2 (*(volatile unsigned *)0x51000024) //Timer count buffer 2
267 #define rTCMPB2 (*(volatile unsigned *)0x51000028) //Timer compare buffer 2
268 #define rTCNTO2 (*(volatile unsigned *)0x5100002c) //Timer count observation 2
269 #define rTCNTB3 (*(volatile unsigned *)0x51000030) //Timer count buffer 3
270 #define rTCMPB3 (*(volatile unsigned *)0x51000034) //Timer compare buffer 3
271 #define rTCNTO3 (*(volatile unsigned *)0x51000038) //Timer count observation 3
272 #define rTCNTB4 (*(volatile unsigned *)0x5100003c) //Timer count buffer 4
273 #define rTCNTO4 (*(volatile unsigned *)0x51000040) //Timer count observation 4
274
275
276 // USB DEVICE
277 #ifdef __BIG_ENDIAN
278
279 #define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000143) //Function address
280 #define rPWR_REG (*(volatile unsigned char *)0x52000147) //Power management
281 #define rEP_INT_REG (*(volatile unsigned char *)0x5200014b) //EP Interrupt pending and clear
282 #define rUSB_INT_REG (*(volatile unsigned char *)0x5200015b) //USB Interrupt pending and clear
283 #define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015f) //Interrupt enable
284 #define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016f)
285 #define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000173) //Frame number lower byte
286 #define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000177) //Frame number higher byte
287 #define rINDEX_REG (*(volatile unsigned char *)0x5200017b) //Register index
288 #define rMAXP_REG (*(volatile unsigned char *)0x52000183) //Endpoint max packet
289 #define rEP0_CSR (*(volatile unsigned char *)0x52000187) //Endpoint 0 status
290 #define rIN_CSR1_REG (*(volatile unsigned char *)0x52000187) //In endpoint control status
291 #define rIN_CSR2_REG (*(volatile unsigned char *)0x5200018b)
292 #define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000193) //Out endpoint control status
293 #define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000197)
294 #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x5200019b) //Endpoint out write count
295 #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019f)
296 #define rEP0_FIFO (*(volatile unsigned char *)0x520001c3) //Endpoint 0 FIFO
297 #define rEP1_FIFO (*(volatile unsigned char *)0x520001c7) //Endpoint 1 FIFO
298 #define rEP2_FIFO (*(volatile unsigned char *)0x520001cb) //Endpoint 2 FIFO
299 #define rEP3_FIFO (*(volatile unsigned char *)0x520001cf) //Endpoint 3 FIFO
300 #define rEP4_FIFO (*(volatile unsigned char *)0x520001d3) //Endpoint 4 FIFO
301 #define rEP1_DMA_CON (*(volatile unsigned char *)0x52000203) //EP1 DMA interface control
302 #define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000207) //EP1 DMA Tx unit counter
303 #define rEP1_DMA_FIFO (*(volatile unsigned char *)0x5200020b) //EP1 DMA Tx FIFO counter
304 #define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020f) //EP1 DMA total Tx counter
305 #define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000213)
306 #define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000217)
307 #define rEP2_DMA_CON (*(volatile unsigned char *)0x5200021b) //EP2 DMA interface control
308 #define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021f) //EP2 DMA Tx unit counter
309 #define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000223) //EP2 DMA Tx FIFO counter
310 #define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000227) //EP2 DMA total Tx counter
311 #define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x5200022b)
312 #define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022f)
313 #define rEP3_DMA_CON (*(volatile unsigned char *)0x52000243) //EP3 DMA interface control
314 #define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000247) //EP3 DMA Tx unit counter
315 #define rEP3_DMA_FIFO (*(volatile unsigned char *)0x5200024b) //EP3 DMA Tx FIFO counter
316 #define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024f) //EP3 DMA total Tx counter
317 #define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000253)
318 #define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000257)
319 #define rEP4_DMA_CON (*(volatile unsigned char *)0x5200025b) //EP4 DMA interface control
320 #define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025f) //EP4 DMA Tx unit counter
321 #define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000263) //EP4 DMA Tx FIFO counter
322 #define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000267) //EP4 DMA total Tx counter
323 #define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x5200026b)
324 #define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026f)
325
326 #else // Little Endian
327 #define rFUNC_ADDR_REG (*(volatile unsigned char *)0x52000140) //Function address
328 #define rPWR_REG (*(volatile unsigned char *)0x52000144) //Power management
329 #define rEP_INT_REG (*(volatile unsigned char *)0x52000148) //EP Interrupt pending and clear
330 #define rUSB_INT_REG (*(volatile unsigned char *)0x52000158) //USB Interrupt pending and clear
331 #define rEP_INT_EN_REG (*(volatile unsigned char *)0x5200015c) //Interrupt enable
332 #define rUSB_INT_EN_REG (*(volatile unsigned char *)0x5200016c)
333 #define rFRAME_NUM1_REG (*(volatile unsigned char *)0x52000170) //Frame number lower byte
334 #define rFRAME_NUM2_REG (*(volatile unsigned char *)0x52000174) //Frame number higher byte
335 #define rINDEX_REG (*(volatile unsigned char *)0x52000178) //Register index
336 #define rMAXP_REG (*(volatile unsigned char *)0x52000180) //Endpoint max packet
337 #define rEP0_CSR (*(volatile unsigned char *)0x52000184) //Endpoint 0 status
338 #define rIN_CSR1_REG (*(volatile unsigned char *)0x52000184) //In endpoint control status
339 #define rIN_CSR2_REG (*(volatile unsigned char *)0x52000188)
340 #define rOUT_CSR1_REG (*(volatile unsigned char *)0x52000190) //Out endpoint control status
341 #define rOUT_CSR2_REG (*(volatile unsigned char *)0x52000194)
342 #define rOUT_FIFO_CNT1_REG (*(volatile unsigned char *)0x52000198) //Endpoint out write count
343 #define rOUT_FIFO_CNT2_REG (*(volatile unsigned char *)0x5200019c)
344 #define rEP0_FIFO (*(volatile unsigned char *)0x520001c0) //Endpoint 0 FIFO
345 #define rEP1_FIFO (*(volatile unsigned char *)0x520001c4) //Endpoint 1 FIFO
346 #define rEP2_FIFO (*(volatile unsigned char *)0x520001c8) //Endpoint 2 FIFO
347 #define rEP3_FIFO (*(volatile unsigned char *)0x520001cc) //Endpoint 3 FIFO
348 #define rEP4_FIFO (*(volatile unsigned char *)0x520001d0) //Endpoint 4 FIFO
349 #define rEP1_DMA_CON (*(volatile unsigned char *)0x52000200) //EP1 DMA interface control
350 #define rEP1_DMA_UNIT (*(volatile unsigned char *)0x52000204) //EP1 DMA Tx unit counter
351 #define rEP1_DMA_FIFO (*(volatile unsigned char *)0x52000208) //EP1 DMA Tx FIFO counter
352 #define rEP1_DMA_TTC_L (*(volatile unsigned char *)0x5200020c) //EP1 DMA total Tx counter
353 #define rEP1_DMA_TTC_M (*(volatile unsigned char *)0x52000210)
354 #define rEP1_DMA_TTC_H (*(volatile unsigned char *)0x52000214)
355 #define rEP2_DMA_CON (*(volatile unsigned char *)0x52000218) //EP2 DMA interface control
356 #define rEP2_DMA_UNIT (*(volatile unsigned char *)0x5200021c) //EP2 DMA Tx unit counter
357 #define rEP2_DMA_FIFO (*(volatile unsigned char *)0x52000220) //EP2 DMA Tx FIFO counter
358 #define rEP2_DMA_TTC_L (*(volatile unsigned char *)0x52000224) //EP2 DMA total Tx counter
359 #define rEP2_DMA_TTC_M (*(volatile unsigned char *)0x52000228)
360 #define rEP2_DMA_TTC_H (*(volatile unsigned char *)0x5200022c)
361 #define rEP3_DMA_CON (*(volatile unsigned char *)0x52000240) //EP3 DMA interface control
362 #define rEP3_DMA_UNIT (*(volatile unsigned char *)0x52000244) //EP3 DMA Tx unit counter
363 #define rEP3_DMA_FIFO (*(volatile unsigned char *)0x52000248) //EP3 DMA Tx FIFO counter
364 #define rEP3_DMA_TTC_L (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter
365 #define rEP3_DMA_TTC_M (*(volatile unsigned char *)0x52000250)
366 #define rEP3_DMA_TTC_H (*(volatile unsigned char *)0x52000254)
367 #define rEP4_DMA_CON (*(volatile unsigned char *)0x52000258) //EP4 DMA interface control
368 #define rEP4_DMA_UNIT (*(volatile unsigned char *)0x5200025c) //EP4 DMA Tx unit counter
369 #define rEP4_DMA_FIFO (*(volatile unsigned char *)0x52000260) //EP4 DMA Tx FIFO counter
370 #define rEP4_DMA_TTC_L (*(volatile unsigned char *)0x52000264) //EP4 DMA total Tx counter
371 #define rEP4_DMA_TTC_M (*(volatile unsigned char *)0x52000268)
372 #define rEP4_DMA_TTC_H (*(volatile unsigned char *)0x5200026c)
373 #endif // __BIG_ENDIAN
374
375
376 // WATCH DOG TIMER
377 #define rWTCON (*(volatile unsigned *)0x53000000) //Watch-dog timer mode
378 #define rWTDAT (*(volatile unsigned *)0x53000004) //Watch-dog timer data
379 #define rWTCNT (*(volatile unsigned *)0x53000008) //Eatch-dog timer count
380
381
382 // IIC
383 #define rIICCON (*(volatile unsigned *)0x54000000) //IIC control
384 #define rIICSTAT (*(volatile unsigned *)0x54000004) //IIC status
385 #define rIICADD (*(volatile unsigned *)0x54000008) //IIC address
386 #define rIICDS (*(volatile unsigned *)0x5400000c) //IIC data shift
387 #define rIICLC (*(volatile unsigned *)0x54000010) //IIC multi-master line control
388
389
390 // IIS
391 #define rIISCON (*(volatile unsigned *)0x55000000) //IIS Control
392 #define rIISMOD (*(volatile unsigned *)0x55000004) //IIS Mode
393 #define rIISPSR (*(volatile unsigned *)0x55000008) //IIS Prescaler
394 #define rIISFCON (*(volatile unsigned *)0x5500000c) //IIS FIFO control
395 #ifdef __BIG_ENDIAN
396 #define IISFIFO ((volatile unsigned short *)0x55000012) //IIS FIFO entry
397 #else //Little Endian
398 #define IISFIFO ((volatile unsigned short *)0x55000010) //IIS FIFO entry
399 #endif
400
401
402 //AC97, Added for S3C2440A
403 #define rAC_GLBCTRL *(volatile unsigned *)0x5b000000
404 #define rAC_GLBSTAT *(volatile unsigned *)0x5b000004
405 #define rAC_CODEC_CMD *(volatile unsigned *)0x5b000008
406 #define rAC_CODEC_STAT *(volatile unsigned *)0x5b00000C
407 #define rAC_PCMADDR *(volatile unsigned *)0x5b000010
408 #define rAC_MICADDR *(volatile unsigned *)0x5b000014
409 #define rAC_PCMDATA *(volatile unsigned *)0x5b000018
410 #define rAC_MICDATA *(volatile unsigned *)0x5b00001C
411
412 #define AC_PCMDATA 0x5b000018
413 #define AC_MICDATA 0x5b00001C
414
415 // I/O PORT
416 #define rGPACON (*(volatile unsigned *)0x56000000) //Port A control
417 #define rGPADAT (*(volatile unsigned *)0x56000004) //Port A data
418
419 #define rGPBCON (*(volatile unsigned *)0x56000010) //Port B control
420 #define rGPBDAT (*(volatile unsigned *)0x56000014) //Port B data
421 #define rGPBUP (*(volatile unsigned *)0x56000018) //Pull-up control B
422
423 #define rGPCCON (*(volatile unsigned *)0x56000020) //Port C control
424 #define rGPCDAT (*(volatile unsigned *)0x56000024) //Port C data
425 #define rGPCUP (*(volatile unsigned *)0x56000028) //Pull-up control C
426
427 #define rGPDCON (*(volatile unsigned *)0x56000030) //Port D control
428 #define rGPDDAT (*(volatile unsigned *)0x56000034) //Port D data
429 #define rGPDUP (*(volatile unsigned *)0x56000038) //Pull-up control D
430
431 #define rGPECON (*(volatile unsigned *)0x56000040) //Port E control
432 #define rGPEDAT (*(volatile unsigned *)0x56000044) //Port E data
433 #define rGPEUP (*(volatile unsigned *)0x56000048) //Pull-up control E
434
435 #define rGPFCON (*(volatile unsigned *)0x56000050) //Port F control
436 #define rGPFDAT (*(volatile unsigned *)0x56000054) //Port F data
437 #define rGPFUP (*(volatile unsigned *)0x56000058) //Pull-up control F
438
439 #define rGPGCON (*(volatile unsigned *)0x56000060) //Port G control
440 #define rGPGDAT (*(volatile unsigned *)0x56000064) //Port G data
441 #define rGPGUP (*(volatile unsigned *)0x56000068) //Pull-up control G
442
443 #define rGPHCON (*(volatile unsigned *)0x56000070) //Port H control
444 #define rGPHDAT (*(volatile unsigned *)0x56000074) //Port H data
445 #define rGPHUP (*(volatile unsigned *)0x56000078) //Pull-up control H
446
447 #define rGPJCON (*(volatile unsigned *)0x560000d0) //Port J control
448 #define rGPJDAT (*(volatile unsigned *)0x560000d4) //Port J data
449 #define rGPJUP (*(volatile unsigned *)0x560000d8) //Pull-up control J
450
451 #define rMISCCR (*(volatile unsigned *)0x56000080) //Miscellaneous control
452 #define rDCLKCON (*(volatile unsigned *)0x56000084) //DCLK0/1 control
453 #define rEXTINT0 (*(volatile unsigned *)0x56000088) //External interrupt control register 0
454 #define rEXTINT1 (*(volatile unsigned *)0x5600008c) //External interrupt control register 1
455 #define rEXTINT2 (*(volatile unsigned *)0x56000090) //External interrupt control register 2
456 #define rEINTFLT0 (*(volatile unsigned *)0x56000094) //Reserved
457 #define rEINTFLT1 (*(volatile unsigned *)0x56000098) //Reserved
458 #define rEINTFLT2 (*(volatile unsigned *)0x5600009c) //External interrupt filter control register 2
459 #define rEINTFLT3 (*(volatile unsigned *)0x560000a0) //External interrupt filter control register 3
460 #define rEINTMASK (*(volatile unsigned *)0x560000a4) //External interrupt mask
461 #define rEINTPEND (*(volatile unsigned *)0x560000a8) //External interrupt pending
462 #define rGSTATUS0 (*(volatile unsigned *)0x560000ac) //External pin status
463 #define rGSTATUS1 (*(volatile unsigned *)0x560000b0) //Chip ID(0x32440000)
464 #define rGSTATUS2 (*(volatile unsigned *)0x560000b4) //Reset type
465 #define rGSTATUS3 (*(volatile unsigned *)0x560000b8) //Saved data0(32-bit) before entering POWER_OFF mode
466 #define rGSTATUS4 (*(volatile unsigned *)0x560000bc) //Saved data0(32-bit) before entering POWER_OFF mode
467
468 // Added for 2440
469 #define rFLTOUT (*(volatile unsigned *)0x560000c0) // Filter output(Read only)
470 #define rDSC0 (*(volatile unsigned *)0x560000c4) // Strength control register 0
471 #define rDSC1 (*(volatile unsigned *)0x560000c8) // Strength control register 1
472 #define rMSLCON (*(volatile unsigned *)0x560000cc) // Memory sleep control register
473
474 // RTC
475 #ifdef __BIG_ENDIAN
476 #define rRTCCON (*(volatile unsigned char *)0x57000043) //RTC control
477 #define rTICNT (*(volatile unsigned char *)0x57000047) //Tick time count
478 #define rRTCALM (*(volatile unsigned char *)0x57000053) //RTC alarm control
479 #define rALMSEC (*(volatile unsigned char *)0x57000057) //Alarm second
480 #define rALMMIN (*(volatile unsigned char *)0x5700005b) //Alarm minute
481 #define rALMHOUR (*(volatile unsigned char *)0x5700005f) //Alarm Hour
482 #define rALMDATE (*(volatile unsigned char *)0x57000063) //Alarm date //edited by junon
483 #define rALMMON (*(volatile unsigned char *)0x57000067) //Alarm month
484 #define rALMYEAR (*(volatile unsigned char *)0x5700006b) //Alarm year
485 #define rRTCRST (*(volatile unsigned char *)0x5700006f) //RTC round reset
486 #define rBCDSEC (*(volatile unsigned char *)0x57000073) //BCD second
487 #define rBCDMIN (*(volatile unsigned char *)0x57000077) //BCD minute
488 #define rBCDHOUR (*(volatile unsigned char *)0x5700007b) //BCD hour
489 #define rBCDDATE (*(volatile unsigned char *)0x5700007f) //BCD date //edited by junon
490 #define rBCDDAY (*(volatile unsigned char *)0x57000083) //BCD day //edited by junon
491 #define rBCDMON (*(volatile unsigned char *)0x57000087) //BCD month
492 #define rBCDYEAR (*(volatile unsigned char *)0x5700008b) //BCD year
493
494 #else //Little Endian
495 #define rRTCCON (*(volatile unsigned char *)0x57000040) //RTC control
496 #define rTICNT (*(volatile unsigned char *)0x57000044) //Tick time count
497 #define rRTCALM (*(volatile unsigned char *)0x57000050) //RTC alarm control
498 #define rALMSEC (*(volatile unsigned char *)0x57000054) //Alarm second
499 #define rALMMIN (*(volatile unsigned char *)0x57000058) //Alarm minute
500 #define rALMHOUR (*(volatile unsigned char *)0x5700005c) //Alarm Hour
501 #define rALMDATE (*(volatile unsigned char *)0x57000060) //Alarm date // edited by junon
502 #define rALMMON (*(volatile unsigned char *)0x57000064) //Alarm month
503 #define rALMYEAR (*(volatile unsigned char *)0x57000068) //Alarm year
504 #define rRTCRST (*(volatile unsigned char *)0x5700006c) //RTC round reset
505 #define rBCDSEC (*(volatile unsigned char *)0x57000070) //BCD second
506 #define rBCDMIN (*(volatile unsigned char *)0x57000074) //BCD minute
507 #define rBCDHOUR (*(volatile unsigned char *)0x57000078) //BCD hour
508 #define rBCDDATE (*(volatile unsigned char *)0x5700007c) //BCD date //edited by junon
509 #define rBCDDAY (*(volatile unsigned char *)0x57000080) //BCD day //edited by junon
510 #define rBCDMON (*(volatile unsigned char *)0x57000084) //BCD month
511 #define rBCDYEAR (*(volatile unsigned char *)0x57000088) //BCD year
512 #endif //RTC
513
514
515 // ADC
516 #define rADCCON (*(volatile unsigned *)0x58000000) //ADC control
517 #define rADCTSC (*(volatile unsigned *)0x58000004) //ADC touch screen control
518 #define rADCDLY (*(volatile unsigned *)0x58000008) //ADC start or Interval Delay
519 #define rADCDAT0 (*(volatile unsigned *)0x5800000c) //ADC conversion data 0
520 #define rADCDAT1 (*(volatile unsigned *)0x58000010) //ADC conversion data 1
521 #define rADCUPDN (*(volatile unsigned *)0x58000014) //Stylus Up/Down interrupt status
522
523
524 // SPI
525 #define rSPCON0 (*(volatile unsigned *)0x59000000) //SPI0 control
526 #define rSPSTA0 (*(volatile unsigned *)0x59000004) //SPI0 status
527 #define rSPPIN0 (*(volatile unsigned *)0x59000008) //SPI0 pin control
528 #define rSPPRE0 (*(volatile unsigned *)0x5900000c) //SPI0 baud rate prescaler
529 #define rSPTDAT0 (*(volatile unsigned *)0x59000010) //SPI0 Tx data
530 #define rSPRDAT0 (*(volatile unsigned *)0x59000014) //SPI0 Rx data
531
532 #define rSPCON1 (*(volatile unsigned *)0x59000020) //SPI1 control
533 #define rSPSTA1 (*(volatile unsigned *)0x59000024) //SPI1 status
534 #define rSPPIN1 (*(volatile unsigned *)0x59000028) //SPI1 pin control
535 #define rSPPRE1 (*(volatile unsigned *)0x5900002c) //SPI1 baud rate prescaler
536 #define rSPTDAT1 (*(volatile unsigned *)0x59000030) //SPI1 Tx data
537 #define rSPRDAT1 (*(volatile unsigned *)0x59000034) //SPI1 Rx data
538
539
540 // SD Interface
541 #define rSDICON (*(volatile unsigned *)0x5a000000) //SDI control
542 #define rSDIPRE (*(volatile unsigned *)0x5a000004) //SDI baud rate prescaler
543 #define rSDICARG (*(volatile unsigned *)0x5a000008) //SDI command argument
544 #define rSDICCON (*(volatile unsigned *)0x5a00000c) //SDI command control
545 #define rSDICSTA (*(volatile unsigned *)0x5a000010) //SDI command status
546 #define rSDIRSP0 (*(volatile unsigned *)0x5a000014) //SDI response 0
547 #define rSDIRSP1 (*(volatile unsigned *)0x5a000018) //SDI response 1
548 #define rSDIRSP2 (*(volatile unsigned *)0x5a00001c) //SDI response 2
549 #define rSDIRSP3 (*(volatile unsigned *)0x5a000020) //SDI response 3
550 #define rSDIDTIMER (*(volatile unsigned *)0x5a000024) //SDI data/busy timer
551 #define rSDIBSIZE (*(volatile unsigned *)0x5a000028) //SDI block size
552 #define rSDIDCON (*(volatile unsigned *)0x5a00002c) //SDI data control
553 #define rSDIDCNT (*(volatile unsigned *)0x5a000030) //SDI data remain counter
554 #define rSDIDSTA (*(volatile unsigned *)0x5a000034) //SDI data status
555 #define rSDIFSTA (*(volatile unsigned *)0x5a000038) //SDI FIFO status
556 #define rSDIIMSK (*(volatile unsigned *)0x5a00003c) //SDI interrupt mask. edited for 2440A
557
558 #ifdef __BIG_ENDIAN /* edited for 2440A */
559 #define rSDIDAT (*(volatile unsigned *)0x5a00004c) //SDI data
560 #define SDIDAT 0x5a00004c
561 #else // Little Endian
562 #define rSDIDAT (*(volatile unsigned *)0x5a000040) //SDI data
563 #define SDIDAT 0x5a000040
564 #endif //SD Interface
565
566
567 // Exception vector
568 #define pISR_RESET (*(unsigned *)(_ISR_STARTADDRESS+0x0))
569 #define pISR_UNDEF (*(unsigned *)(_ISR_STARTADDRESS+0x4))
570 #define pISR_SWI (*(unsigned *)(_ISR_STARTADDRESS+0x8))
571 #define pISR_PABORT (*(unsigned *)(_ISR_STARTADDRESS+0xc))
572 #define pISR_DABORT (*(unsigned *)(_ISR_STARTADDRESS+0x10))
573 #define pISR_RESERVED (*(unsigned *)(_ISR_STARTADDRESS+0x14))
574 #define pISR_IRQ (*(unsigned *)(_ISR_STARTADDRESS+0x18))
575 #define pISR_FIQ (*(unsigned *)(_ISR_STARTADDRESS+0x1c))
576 // Interrupt vector
577 #define pISR_EINT0 (*(unsigned *)(_ISR_STARTADDRESS+0x20))
578 #define pISR_EINT1 (*(unsigned *)(_ISR_STARTADDRESS+0x24))
579 #define pISR_EINT2 (*(unsigned *)(_ISR_STARTADDRESS+0x28))
580 #define pISR_EINT3 (*(unsigned *)(_ISR_STARTADDRESS+0x2c))
581 #define pISR_EINT4_7 (*(unsigned *)(_ISR_STARTADDRESS+0x30))
582 #define pISR_EINT8_23 (*(unsigned *)(_ISR_STARTADDRESS+0x34))
583 #define pISR_CAM (*(unsigned *)(_ISR_STARTADDRESS+0x38)) // Added for 2440.
584 #define pISR_BAT_FLT (*(unsigned *)(_ISR_STARTADDRESS+0x3c))
585 #define pISR_TICK (*(unsigned *)(_ISR_STARTADDRESS+0x40))
586 #define pISR_WDT_AC97 (*(unsigned *)(_ISR_STARTADDRESS+0x44)) //Changed to pISR_WDT_AC97 for 2440A
587 #define pISR_TIMER0 (*(unsigned *)(_ISR_STARTADDRESS+0x48))
588 #define pISR_TIMER1 (*(unsigned *)(_ISR_STARTADDRESS+0x4c))
589 #define pISR_TIMER2 (*(unsigned *)(_ISR_STARTADDRESS+0x50))
590 #define pISR_TIMER3 (*(unsigned *)(_ISR_STARTADDRESS+0x54))
591 #define pISR_TIMER4 (*(unsigned *)(_ISR_STARTADDRESS+0x58))
592 #define pISR_UART2 (*(unsigned *)(_ISR_STARTADDRESS+0x5c))
593 #define pISR_LCD (*(unsigned *)(_ISR_STARTADDRESS+0x60))
594 #define pISR_DMA0 (*(unsigned *)(_ISR_STARTADDRESS+0x64))
595 #define pISR_DMA1 (*(unsigned *)(_ISR_STARTADDRESS+0x68))
596 #define pISR_DMA2 (*(unsigned *)(_ISR_STARTADDRESS+0x6c))
597 #define pISR_DMA3 (*(unsigned *)(_ISR_STARTADDRESS+0x70))
598 #define pISR_SDI (*(unsigned *)(_ISR_STARTADDRESS+0x74))
599 #define pISR_SPI0 (*(unsigned *)(_ISR_STARTADDRESS+0x78))
600 #define pISR_UART1 (*(unsigned *)(_ISR_STARTADDRESS+0x7c))
601 #define pISR_NFCON (*(unsigned *)(_ISR_STARTADDRESS+0x80)) // Added for 2440.
602 #define pISR_USBD (*(unsigned *)(_ISR_STARTADDRESS+0x84))
603 #define pISR_USBH (*(unsigned *)(_ISR_STARTADDRESS+0x88))
604 #define pISR_IIC (*(unsigned *)(_ISR_STARTADDRESS+0x8c))
605 #define pISR_UART0 (*(unsigned *)(_ISR_STARTADDRESS+0x90))
606 #define pISR_SPI1 (*(unsigned *)(_ISR_STARTADDRESS+0x94))
607 #define pISR_RTC (*(unsigned *)(_ISR_STARTADDRESS+0x98))
608 #define pISR_ADC (*(unsigned *)(_ISR_STARTADDRESS+0x9c))
609
610
611 // PENDING BIT
612 #define BIT_EINT0 (0x1)
613 #define BIT_EINT1 (0x1<<1)
614 #define BIT_EINT2 (0x1<<2)
615 #define BIT_EINT3 (0x1<<3)
616 #define BIT_EINT4_7 (0x1<<4)
617 #define BIT_EINT8_23 (0x1<<5)
618 #define BIT_CAM (0x1<<6) // Added for 2440.
619 #define BIT_BAT_FLT (0x1<<7)
620 #define BIT_TICK (0x1<<8)
621 #define BIT_WDT_AC97 (0x1<<9) // Changed from BIT_WDT to BIT_WDT_AC97 for 2440A
622 #define BIT_TIMER0 (0x1<<10)
623 #define BIT_TIMER1 (0x1<<11)
624 #define BIT_TIMER2 (0x1<<12)
625 #define BIT_TIMER3 (0x1<<13)
626 #define BIT_TIMER4 (0x1<<14)
627 #define BIT_UART2 (0x1<<15)
628 #define BIT_LCD (0x1<<16)
629 #define BIT_DMA0 (0x1<<17)
630 #define BIT_DMA1 (0x1<<18)
631 #define BIT_DMA2 (0x1<<19)
632 #define BIT_DMA3 (0x1<<20)
633 #define BIT_SDI (0x1<<21)
634 #define BIT_SPI0 (0x1<<22)
635 #define BIT_UART1 (0x1<<23)
636 #define BIT_NFCON (0x1<<24) // Added for 2440.
637 #define BIT_USBD (0x1<<25)
638 #define BIT_USBH (0x1<<26)
639 #define BIT_IIC (0x1<<27)
640 #define BIT_UART0 (0x1<<28)
641 #define BIT_SPI1 (0x1<<29)
642 #define BIT_RTC (0x1<<30)
643 #define BIT_ADC (0x1<<31)
644 #define BIT_ALLMSK (0xffffffff)
645
646 #define BIT_SUB_ALLMSK (0x7fff) //Changed from 0x7ff to 0x7fff for 2440A
647 #define BIT_SUB_AC97 (0x1<<14) //Added for 2440A
648 #define BIT_SUB_WDT (0x1<<13) //Added for 2440A
649 #define BIT_SUB_CAM_P (0x1<<12) // edited for 2440A.
650 #define BIT_SUB_CAM_C (0x1<<11) // edited for 2440A
651 #define BIT_SUB_ADC (0x1<<10)
652 #define BIT_SUB_TC (0x1<<9)
653 #define BIT_SUB_ERR2 (0x1<<8)
654 #define BIT_SUB_TXD2 (0x1<<7)
655 #define BIT_SUB_RXD2 (0x1<<6)
656 #define BIT_SUB_ERR1 (0x1<<5)
657 #define BIT_SUB_TXD1 (0x1<<4)
658 #define BIT_SUB_RXD1 (0x1<<3)
659 #define BIT_SUB_ERR0 (0x1<<2)
660 #define BIT_SUB_TXD0 (0x1<<1)
661 #define BIT_SUB_RXD0 (0x1<<0)
662
663 //Wait until rINTPND is changed for the case that the ISR is very short.
664 /*
665 #define ClearPending(bit) {/
666 rSRCPND = bit;/
667 rINTPND = bit;/
668 rINTPND;/
669 }
670 */
671
672 #define EnableIrq(bit) rINTMSK &= ~(bit)
673 #define DisableIrq(bit) rINTMSK |= (bit)
674 #define EnableSubIrq(bit) rINTSUBMSK &= ~(bit)
675 #define DisableSubIrq(bit) rINTSUBMSK |= (bit)
676 /*
677 __inline void ClearPending(int bit)
678 {
679 register i;
680 rSRCPND = bit;
681 rINTPND = bit;
682 i = rINTPND;
683 }
684
685 __inline void ClearSubPending(int bit)
686 {
687 register i;
688 rSUBSRCPND = bit;
689 i = rINTPND;
690 } */
691 //Wait until rINTPND is changed for the case that the ISR is very short.
/* 将677~689行代码注释掉，以适应mini2440开发板 */
692
693
694 #ifdef __cplusplus
695 }
696 #endif
697 #endif //__2440ADDR_H__
///////////
include/option.h 为新引入的文件，内容如下：不需任何修改：
1 /**************************************************************
2 NAME: option.h
3 DESC: To measuure the USB download speed, the WDT is used.
4 To measure up to large time, The WDT interrupt is used.
5 HISTORY:
6 Feb.20.2002:Shin, On Pil: Programming start
7 Mar.25.2002:purnnamu: S3C2400X profile.c is ported for S3C2440X.
8 **************************************************************/
9
10 #ifndef __OPTION_H__
11 #define __OPTION_H__
12
13 //--by Customer--
14
15 //#define LCD_N35
16 //#define LCD_L80
17 #define LCD_T35
18 //#define LCD_X35
19 //#define LCD_A70
20 //#define LCD_VGA1024768
21
22 //--end of by Customer--
23
24 #if defined(LCD_N35) + defined(LCD_L80) + defined(LCD_T35) + defined(LCD_A70) + defined(LCD_VGA1024768) + defined(LCD_X35)!= 1
25 #error Must define only one LCD type
26 #endif
27
28 #if defined(LCD_N35)
29
30 #define LCD_WIDTH 240
31 #define LCD_HEIGHT 320
32 #define LCD_PIXCLOCK 4
33
34 #define LCD_RIGHT_MARGIN 36
35 #define LCD_LEFT_MARGIN 19
36 #define LCD_HSYNC_LEN 5
37
38 #define LCD_UPPER_MARGIN 1
39 #define LCD_LOWER_MARGIN 5
40 #define LCD_VSYNC_LEN 1
41
42 #elif defined(LCD_L80)
43 #define LCD_WIDTH 640
44 #define LCD_HEIGHT 480
45 #define LCD_PIXCLOCK 2
46
47 #define LCD_RIGHT_MARGIN 67
48 #define LCD_LEFT_MARGIN 40
49 #define LCD_HSYNC_LEN 31
50
51 #define LCD_UPPER_MARGIN 25
52 #define LCD_LOWER_MARGIN 5
53 #define LCD_VSYNC_LEN 1
54
55
56 #elif defined(LCD_T35)
57 #define LCD_WIDTH 240
58 #define LCD_HEIGHT 320
59 #define LCD_PIXCLOCK 4
60
61 #define LCD_RIGHT_MARGIN 25
62 #define LCD_LEFT_MARGIN 0
63 #define LCD_HSYNC_LEN 4
64
65 #define LCD_UPPER_MARGIN 1
66 #define LCD_LOWER_MARGIN 4
67 #define LCD_VSYNC_LEN 1
68 #define LCD_CON5 ( (1 << 11)| (1<<0) | (1 << 8) | (1 << 6) | (1 << 9) | ( 1<< 10))
69
70 #elif defined(LCD_X35)
71 #define LCD_WIDTH 240
72 #define LCD_HEIGHT 320
73 #define LCD_PIXCLOCK 4
74
75 #define LCD_RIGHT_MARGIN 25
76 #define LCD_LEFT_MARGIN 0
77 #define LCD_HSYNC_LEN 4
78
79 #define LCD_UPPER_MARGIN 0
80 #define LCD_LOWER_MARGIN 4
81 #define LCD_VSYNC_LEN 9
82 #define LCD_CON5 ( (1 << 11)| (1<<0) | (1 << 8) | (1 << 6) | (1 << 9) | ( 1<< 10))
83
84 #elif defined(LCD_A70)
85 #define LCD_WIDTH 800
86 #define LCD_HEIGHT 480
87 #define LCD_PIXCLOCK 2
88
89 #define LCD_RIGHT_MARGIN 67
90 #define LCD_LEFT_MARGIN 40
91 #define LCD_HSYNC_LEN 31
92
93 #define LCD_UPPER_MARGIN 25
94 #define LCD_LOWER_MARGIN 5
95 #define LCD_VSYNC_LEN 1
96
97 #elif defined(LCD_VGA1024768)
98 #define LCD_WIDTH 1024
99 #define LCD_HEIGHT 768
100 #define LCD_PIXCLOCK 2
101
102 #define LCD_RIGHT_MARGIN 15
103 #define LCD_LEFT_MARGIN 199
104 #define LCD_HSYNC_LEN 15
105
106 #define LCD_UPPER_MARGIN 1
107 #define LCD_LOWER_MARGIN 1
108 #define LCD_VSYNC_LEN 1
109 #define LCD_CON5 ( (1 << 11)| (1<<0) )
110
111 #endif
112
113
114 #define MEGA (1000000)
115
116 #define FIN (12000000)
117 //#define FIN (16934400)
118 //#define FCLK 304800000
119 //#define FCLK 296352000
120 //#define FCLK 271500000
121 //#define FCLK 200000000
122 //#define FCLK 240000000
123 //#define FCLK 300000000
124 //#define FCLK 320000000
125 //#define FCLK 330000000
126 //#define FCLK 340000000
127 //#define FCLK 350000000
128 //#define FCLK 360000000
129 //#define FCLK 380000000
130 //#define FCLK 400000000
131 /*
132 // Main clock
133 #if FIN==12000000
134 #if (FCLK==200000000)
135 #define HCLK (FCLK/2)
136 #define PCLK (HCLK/2)
137 #elif (FCLK==304800000) || (FCLK==271500000) || (FCLK==240000000)
138 #define HCLK (FCLK/3)
139 #define PCLK (HCLK/2)
140 #elif (FCLK==360000000) || (FCLK==380000000) || (FCLK==400000000)
141 #define HCLK (FCLK/4)
142 #define PCLK (HCLK/2)
143 #elif (FCLK==340000000) || (FCLK==350000000) || (FCLK==300000000) || (FCLK==320000000) || (FCLK==330000000)
144 #define HCLK (FCLK/4)
145 #define PCLK (HCLK/1)
146 #endif
147 #else //FIN=16.9344MHz
148 #if FCLK==266716800
149 #define HCLK (FCLK/2)
150 #define PCLK (HCLK/2)
151 #elif FCLK==296352000
152 #define HCLK (FCLK/3)
153 #define PCLK (HCLK/2)
154 #elif FCLK==399651840
155 #define HCLK (FCLK/3)
156 #define PCLK (HCLK/2)
157 #endif
158 #endif
159
160 // USB clock
161 #define UCLK 48000000
162 */
163 //use variable
164 #ifdef GLOBAL_CLK
165 U32 FCLK;
166 U32 HCLK;
167 U32 PCLK;
168 U32 UCLK;
169 #else
170 extern unsigned int FCLK;
171 extern unsigned int HCLK;
172 extern unsigned int PCLK;
173 extern unsigned int UCLK;
174 #endif
175
176 // BUSWIDTH : 16,32
177 #define BUSWIDTH (32)
178
179 //64MB
180 // 0x30000000 ~ 0x30ffffff : Download Area (16MB) Cacheable
181 // 0x31000000 ~ 0x33feffff : Non-Cacheable Area
182 // 0x33ff0000 ~ 0x33ff47ff : Heap & RW Area
183 // 0x33ff4800 ~ 0x33ff7fff : FIQ ~ User Stack Area
184 // 0x33ff8000 ~ 0x33fffeff : Not Useed Area
185 // 0x33ffff00 ~ 0x33ffffff : Exception & ISR Vector Table
186
187 #define _RAM_STARTADDRESS 0x30000000
188 #define _ISR_STARTADDRESS 0x33ffff00
189 #define _MMUTT_STARTADDRESS 0x33ff8000
190 #define _STACK_BASEADDRESS 0x33ff8000
191 #define HEAPEND 0x33ff0000
192 #define _NONCACHE_STARTADDRESS 0x31000000
193
194 //If you use ADS1.x, please define ADS10
195 #define ADS10 1
196
197 //USB Device Options
198 #define USBDMA 1 //1->0
199 #define USBDMA_DEMAND 0 //the downloadFileSize should be (64*n)
200 #define BULK_PKT_SIZE 64
201
202 // note: makefile,option.a should be changed
203
204 //USER test program
205
206
207 #endif /*__OPTION_H__*/
//////////////
参见前面在源代码中搜索到的和CONFIG_S3C2410，和CONFIG_SMDK2410的引用，
需要将 cpu/arm920t/interrupts.c ，cpu/arm920t/serial.c 中关于 对头文件 s3c2410.h 的包含指令改为对 s3c2440.h的包含指令，具体如下：
cpu/arm920t/interrupts.c
1 /*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH
4 * Marius Groeger
5 *
6 * (C) Copyright 2002
7 * Sysgo Real-Time Solutions, GmbH
8 * Alex Zuepke
9 *
10 * (C) Copyright 2002
11 * Gary Jennejohn, DENX Software Engineering,
12 *
13 * See file CREDITS for list of people who contributed to this
14 * project.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 * MA 02111-1307 USA
30 */
31
32 #include "armboot.h"
33 #include "arm920t.h"
34 #if defined(CONFIG_S3C2400)
35 #include "s3c2400.h"
36 #elif defined(CONFIG_S3C2410)
37 #include "s3c2410.h"
38 #elif defined(CONFIG_S3C2440) /* snallie, Tue Mar 15 16:06:21 CST 2011 */
39 #include "s3c2440.h" /* snallie, attention that the include object maybe s3c2440.h ! */
/*
* 38~39为新加入的指令，在配置文件include/configs/config_mini2440.h 中将定义宏CONFIG_S3C2440 ，这样将会使s3c2440.h被包含进来
* 因为MINI2440板上的处理器为S3C2440,所以s3c2440.h是应该被包含进来的头文件，本文件只修改这一处。
*/
40 #endif
41
42 #include "ptregs.h"
43
44 extern void reset_cpu(ulong addr);
45
46 /* for 10 ms clock period @ 50 MHz with 4 bit divider = 1/2 (default) */
47 /* and prescaler = 16 */
48 #define TIMER_LOAD_VAL 15625
49
50 /* macro to read the 16 bit timer */
51 #define READ_TIMER (rTCNTO4 & 0xffff)
52
53 #ifdef CONFIG_USE_IRQ
54 /* enable IRQ interrupts */
55 void enable_interrupts (void)
56 {
57 unsigned long temp;
58 __asm__ __volatile__("mrs %0, cpsr/n"
59 "bic %0, %0, #0x80/n"
60 "msr cpsr_c, %0"
61 : "=r" (temp)
62 :
63 : "memory");
64 }
65
66
67 /*
68 * disable IRQ/FIQ interrupts
69 * returns true if interrupts had been enabled before we disabled them
70 */
71 int disable_interrupts (void)
72 {
73 unsigned long old,temp;
74 __asm__ __volatile__("mrs %0, cpsr/n"
75 "orr %1, %0, #0xc0/n"
76 "msr cpsr_c, %1"
77 : "=r" (old), "=r" (temp)
78 :
79 : "memory");
80 return (old & 0x80) == 0;
81 }
82 #else
83 void enable_interrupts (void)
84 {
85 return;
86 }
87 int disable_interrupts (void)
88 {
89 return 0;
90 }
91 #endif
92
93
94
95 void bad_mode(void)
96 {
97 panic("Resetting CPU .../n");
98 reset_cpu(0);
99 }
100
101 void show_regs(struct pt_regs * regs)
102 {
103 unsigned long flags;
104 const char *processor_modes[]=
105 { "USER_26", "FIQ_26" , "IRQ_26" , "SVC_26" , "UK4_26" , "UK5_26" , "UK6_26" , "UK7_26" ,
106 "UK8_26" , "UK9_26" , "UK10_26", "UK11_26", "UK12_26", "UK13_26", "UK14_26", "UK15_26",
107 "USER_32", "FIQ_32" , "IRQ_32" , "SVC_32" , "UK4_32" , "UK5_32" , "UK6_32" , "ABT_32" ,
108 "UK8_32" , "UK9_32" , "UK10_32", "UND_32" , "UK12_32", "UK13_32", "UK14_32", "SYS_32"
109 };
110
111 flags = condition_codes(regs);
112
113 printf("pc : [<%08lx>] lr : [<%08lx>]/n"
114 "sp : %08lx ip : %08lx fp : %08lx/n",
115 instruction_pointer(regs),
116 regs->ARM_lr, regs->ARM_sp,
117 regs->ARM_ip, regs->ARM_fp);
118 printf("r10: %08lx r9 : %08lx r8 : %08lx/n",
119 regs->ARM_r10, regs->ARM_r9,
120 regs->ARM_r8);
121 printf("r7 : %08lx r6 : %08lx r5 : %08lx r4 : %08lx/n",
122 regs->ARM_r7, regs->ARM_r6,
123 regs->ARM_r5, regs->ARM_r4);
124 printf("r3 : %08lx r2 : %08lx r1 : %08lx r0 : %08lx/n",
125 regs->ARM_r3, regs->ARM_r2,
126 regs->ARM_r1, regs->ARM_r0);
127 printf("Flags: %c%c%c%c",
128 flags & CC_N_BIT ? 'N' : 'n',
129 flags & CC_Z_BIT ? 'Z' : 'z',
130 flags & CC_C_BIT ? 'C' : 'c',
131 flags & CC_V_BIT ? 'V' : 'v');
132 printf(" IRQs %s FIQs %s Mode %s%s/n",
133 interrupts_enabled(regs) ? "on" : "off",
134 fast_interrupts_enabled(regs) ? "on" : "off",
135 processor_modes[processor_mode(regs)],
136 thumb_mode(regs) ? " (T)" : "");
137 }
138
139 void do_undefined_instruction(struct pt_regs *pt_regs)
140 {
141 printf("undefined instruction/n");
142 show_regs(pt_regs);
143 bad_mode();
144 }
145
146 void do_software_interrupt(struct pt_regs *pt_regs)
147 {
148 printf("software interrupt/n");
149 show_regs(pt_regs);
150 bad_mode();
151 }
152
153 void do_prefetch_abort(struct pt_regs *pt_regs)
154 {
155 printf("prefetch abort/n");
156 show_regs(pt_regs);
157 bad_mode();
158 }
159
160 void do_data_abort(struct pt_regs *pt_regs)
161 {
162 printf("data abort/n");
163 show_regs(pt_regs);
164 bad_mode();
165 }
166
167 void do_not_used(struct pt_regs *pt_regs)
168 {
169 printf("not used/n");
170 show_regs(pt_regs);
171 bad_mode();
172 }
173
174 void do_fiq(struct pt_regs *pt_regs)
175 {
176 printf("fast interrupt request/n");
177 show_regs(pt_regs);
178 bad_mode();
179 }
180
181 void do_irq(struct pt_regs *pt_regs)
182 {
183 printf("interrupt request/n");
184 show_regs(pt_regs);
185 bad_mode();
186 }
187
188 static ulong timestamp;
189 static ulong lastdec;
190
191 extern void interrupt_init (bd_t *bd)
192 {
193 /* use PWM Timer 4 because it has no output */
194 /* prescaler for Timer 4 is 16 */
195 rTCFG0 = 0x0f00;
196 /* load value for 10 ms timeout, assumes PCLK is 30 MHz !! */
197 lastdec = rTCNTB4 = TIMER_LOAD_VAL;
198 /* auto load, manual update of Timer 4 */
199 rTCON = 0x600000;
200 /* auto load, start Timer 4 */
201 rTCON = 0x500000;
202 timestamp = 0;
203 }
204
205 /*
206 * timer without interrupts
207 */
208
209 void reset_timer(void)
210 {
211 reset_timer_masked();
212 }
213
214 ulong get_timer (ulong base)
215 {
216 return get_timer_masked() - base;
217 }
218
219 void set_timer (ulong t)
220 {
221 timestamp = t;
222 }
223
224 void udelay(unsigned long usec)
225 {
226 ulong tmo;
227
228 tmo = usec / 1000;
229 tmo *= CFG_HZ;
230 tmo /= 1000;
231
232 tmo += get_timer(0);
233
234 while(get_timer_masked() < tmo)
235 /*NOP*/;
236 }
237
238 void reset_timer_masked(void)
239 {
240 /* reset time */
241 lastdec = READ_TIMER;
242 timestamp = 0;
243 }
244
245 ulong get_timer_masked(void)
246 {
247 ulong now = READ_TIMER;
248
249 if (lastdec >= now)
250 {
251 /* normal mode */
252 timestamp += lastdec - now;
253 } else {
254 /* we have an overflow ... */
255 timestamp += lastdec + TIMER_LOAD_VAL - now;
256 }
257 lastdec = now;
258
259 return timestamp;
260 }
261
262 void udelay_masked(unsigned long usec)
263 {
264 ulong tmo;
265
266 tmo = usec / 1000;
267 tmo *= CFG_HZ;
268 tmo /= 1000;
269
270 reset_timer_masked();
271
272 while(get_timer_masked() < tmo)
273 /*NOP*/;
274 }
275
//////////////
cpu/arm920t/serial.c的修改：
1 /*
2 * (C) Copyright 2002
3 * Gary Jennejohn, DENX Software Engineering,
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 *
19 */
20
21 #include "armboot.h"
22 #include "arm920t.h"
23 #if defined(CONFIG_S3C2400)
24 #include "s3c2400.h"
25 #elif defined(CONFIG_S3C2410)
26 #include "s3c2410.h"
27 #elif defined(CONFIG_S3C2440) /* snallie, Tue Mar 15 16:06:21 CST 2011 */
28 #include "s3c2440.h" /* snallie, attention that the include object maybe s3c2440.h ! */
/*
* 27~28为新加入的指令，在配置文件include/configs/config_mini2440.h 中将定义宏CONFIG_S3C2440 ，这样将会使s3c2440.h被包含进来
* 因为MINI2440板上的处理器为S3C2440,所以s3c2440.h是应该被包含进来的头文件，本文件只修改这一处。
*/
29 #endif
30
31 unsigned int br[] = {1562, 780, 390, 194, 32, 15};
32 void serial_setbrg(bd_t *bd, int baudrate)
33 {
34 int i;
35 unsigned int reg = 0;
36
37 #if defined(CONFIG_SMDK2400)
38 /* this assumes a PCLK of 50 MHz */
39 /* value is calculated so : (int)(PCLK/16./baudrate) -1 */
40 if (baudrate == 1200) reg = 2603;
41 else if (baudrate == 9600) reg = 325;
42 else if (baudrate == 19200) reg = 162;
43 else if (baudrate == 38400) reg = 80;
44 else if (baudrate == 57600) reg = 53;
45 else if (baudrate == 115200) reg = 26;
46 else hang();
47 #elif defined(CONFIG_SMDK2410) || defined(CONFIG_MINI2440) /* snallie */
/*
* 47行追加 || defined(CONFIG_MINI2440)，在配置文件include/configs/config_mini2440.h 中将定义宏CONFIG_MINI2440 ，这样将会使得
* 下面的串口的波特率被设定为正确的值。
*/
48 /* this assumes a PCLK of 50.7 MHz */
49 /* value is calculated so : (int)(PCLK/16./baudrate) -1 */
50 if (baudrate == 1200) reg = 2639;
51 else if (baudrate == 9600) reg = 329;
52 else if (baudrate == 19200) reg = 164;
53 else if (baudrate == 38400) reg = 82;
54 else if (baudrate == 57600) reg = 54;
55 else if (baudrate == 115200) reg = 27;
56 else hang();
57 #else
58 # error Bord config missing
59 #endif
60
61 #ifdef CONFIG_SERIAL1
62 /* FIFO enable, Tx/Rx FIFO clear */
63 rUFCON0 = 0x06;
64 rUMCON0 = 0x0;
65 /* Normal,No parity,1 stop,8 bit */
66 rULCON0 = 0x3;
67 /*
68 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
69 * normal,interrupt or polling
70 */
71 rUCON0 = 0x245;
72 rUBRDIV0 = reg;
73
74 for(i=0;i<100;i++);
75 #elif CONFIG_SERIAL2
76 /* FIFO enable, Tx/Rx FIFO clear */
77 rUFCON1 = 0x06;
78 rUMCON1 = 0x0;
79 /* Normal,No parity,1 stop,8 bit */
80 rULCON1 = 0x3;
81 /*
82 * tx=level,rx=edge,disable timeout int.,enable rx error int.,
83 * normal,interrupt or polling
84 */
85 rUCON1 = 0x245;
86 rUBRDIV1 = reg;
87
88 for(i=0;i<100;i++);
89 #else
90 #error "Bad: you didn't configure serial ..."
91 #endif
92 }
93
94 /*
95 * Initialise the serial port with the given baudrate. The settings
96 * are always 8 data bits, no parity, 1 stop bit, no start bits.
97 *
98 */
99 void serial_init(bd_t *bd)
100 {
101 const char *baudrate;
102
103 if ((baudrate = getenv(bd, "baudrate")) != 0)
104 bd->bi_baudrate = simple_strtoul(baudrate, NULL, 10);
105
106 serial_setbrg(bd, bd->bi_baudrate);
107 }
108
109 /*
110 * Read a single byte from the serial port. Returns 1 on success, 0
111 * otherwise. When the function is succesfull, the character read is
112 * written into its argument c.
113 */
114 int serial_getc(void)
115 {
116 #ifdef CONFIG_SERIAL1
117 while(!(rUTRSTAT0 & 0x1))
118 ;
119
120 return rURXH0 & 0xff;
121 #elif CONFIG_SERIAL2
122 while(!(rUTRSTAT1 & 0x1))
123 ;
124
125 return rURXH1 & 0xff;
126 #endif
127 }
128
129
130 /*
131 * Output a single byte to the serial port.
132 */
133 void serial_putc(const char c)
134 {
135 #ifdef CONFIG_SERIAL1
136 /* wait for room in the tx FIFO on SERIAL1 */
137 while(!(rUTRSTAT0 & 0x2))
138 ;
139
140 rUTXH0 = c;
141 #elif CONFIG_SERIAL2
142 /* wait for room in the tx FIFO on SERIAL2 */
143 while(!(rUTRSTAT1 & 0x2))
144 ;
145
146 rUTXH1= c;
147 #endif
148
149 /* If /n, also do /r */
150 if(c == '/n')
151 serial_putc('/r');
152 }
153
154 /*
155 * Test whether a character is in the RX buffer
156 */
157 int serial_tstc(void)
158 {
159 #ifdef CONFIG_SERIAL1
160 return rUTRSTAT0 & 0x1;
161 #elif CONFIG_SERIAL2
162 return rUTRSTAT1 & 0x1;
163 #endif
164 }
165
///////////////
修改include/configs/config_mini2440.h
将CONFIG_S3C2410，CONFIG_SMDK2410注释掉，加入CONFIG_S3C2440和CONFIG_MINI2440的宏定义以及其他一些宏定义和条件编译指令，如下：
1 /*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH
4 * Marius Groeger
5 * Gary Jennejohn
6 * David Mueller
7 *
8 * Configuation settings for the SAMSUNG SMDK2410 board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29 #ifndef __CONFIG_H
30 #define __CONFIG_H
31
32 /*
33 * If we are developing, we might want to start armboot from ram
34 * so we MUST NOT initialize critical regs like mem-timing ...
35 */
36 #define CONFIG_INIT_CRITICAL /* undef for developing */
37
38 /*
39 * High Level Configuration Options
40 * (easy to change)
41 */
42 #define CONFIG_ARM920T 1 /* This is an ARM920T Core */
43 //#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ // snallie
44 //#define CONFIG_SMDK2410 1 /* on an SAMSUNG SMDK2410 Board */ // snallie
45
46 #define CONFIG_S3C2440 1 /* in a SAMSUNG S3C2440 SoC */ // snallie
47 #define CONFIG_MINI2440 1 /* on an FriendlyARM MINI2440 Board */ // snallie
/*
* 43~47 将CONFIG_S3C2410，CONFIG_SMDK2410的宏定义取消，定义新的宏CONFIG_S3C2440，CONFIG_MINI2440
*/
48 #define CONFIG_MINI2440_LED 1 /* snallie */
49 #define CONFIG_MACH_MINI2440 782 // snallie
/*
* 49行定义了MINI2440 的machine_id
*/
50
51 #define USE_920T_MMU 1
52 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
53
54 /*
55 * Size of malloc() pool
56 */
57 #define CONFIG_MALLOC_SIZE (CFG_ENV_SIZE + 128*1024)
58
59 /*
60 * Hardware drivers
61 */
62 #if defined(CONFIG_SMDK2410) // snallie
63 #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
64 #define CS8900_BASE 0x19000300
65 #define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
66 #endif // snallie
67
68 #if defined(CONFIG_MINI2440) // snallie
69 #define CONFIG_DRIVER_DM9000 1 // snallie
70 #define CONFIG_DM9000_USE_16BIT 1
71 //#define CONFIG_DM9000_BUS16 1 /* the Linux driver does accesses as shorts */
72 #define CONFIG_DM9000_BASE 0x20000000
73 #define DM9000_IO 0x20000000
74 #define DM9000_DATA 0x20000004
75 //#define CONFIG_DM9000_DEBUG
76 #endif // snallie
/*
* 62~66行在条件编译下相当于空，68~76定义了DM9000网络芯片的参数，移植DM9000网络芯片驱动时候会用到
*/
77
78 /*
79 * select serial console configuration
80 */
81 #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */
82
83 /* allow to overwrite serial and ethaddr */
84 #define CONFIG_ENV_OVERWRITE
85
86 #define CONFIG_BAUDRATE 115200
87
88 #ifndef USE_920T_MMU
89 #define CONFIG_COMMANDS (CONFIG_CMD_DFL & ~CFG_CMD_CACHE)
90 #else
91 #define CONFIG_COMMANDS (CONFIG_CMD_DFL)
92 #endif
93
94 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
95 #include
96
97 #define CONFIG_BOOTDELAY 3
98 //#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600"
99 #define CONFIG_BOOTARGS "noinitrd root=/dev/mtdblock2 init=/linuxrc console=ttySAC0,115200n8" /* snallie */
100 #define CONFIG_ETHADDR 08:00:3e:26:0a:5b
101 #define CONFIG_NETMASK 255.255.255.0
102 //#define CONFIG_IPADDR 10.0.0.110
103 //#define CONFIG_SERVERIP 10.0.0.1
104 #define CONFIG_IPADDR 192.168.2.2
105 #define CONFIG_SERVERIP 192.168.2.1
106 //#define CONFIG_BOOTFILE "elinos-lart"
107 #define CONFIG_BOOTFILE "uImage110_2440"
108 //#define CONFIG_BOOTCOMMAND "tftp; bootm" // snlalie
109 #define CONFIG_BOOTCOMMAND "nboot" // snallie
/*
* 99行定义了ARMBoot 给Linux kernel 传递的启动参数，100~105定义了网络芯片的物理地址和IP地址信息，107行定义了下载的Linux kernel的文件名
* 格式为uImage格式的。109行定义了默认的内核的启动命令。
*/
110
111 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
112 #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
113 /* what's this ? it's not used anywhere */
114 #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
115 #endif
116
117 /*
118 * Miscellaneous configurable options
119 */
120 #define CFG_LONGHELP /* undef to save memory */
121
122 #if defined(CONFIG_SMDK2410) // snallie
123 #define CFG_PROMPT "SMDK2410 # " /* Monitor Command Prompt */ // snallie
124 #endif // snallie
125
126 #if defined(CONFIG_MINI2440) // snallie
127 #define CFG_PROMPT "ARMboot@MINI2440 # " /* Monitor Command Prompt */ // snallie
128 #endif // snallie
/*
* 126~128行定义了ARMboot的命令提示符。
*/
129
130 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
131 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
132 #define CFG_MAXARGS 16 /* max number of command args */
133 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
134
135 #define CFG_MEMTEST_START 0x30000000 /* memtest works on */
136 #define CFG_MEMTEST_END 0x31F00000 /* 31 MB in DRAM */
137
138 #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
139
140 //#define CFG_LOAD_ADDR 0x31000000 /* default load address */
141 #define CFG_LOAD_ADDR 0x30008000/* default load address*/ // snallie
142 #define CONFIG_LOADADDR CFG_LOAD_ADDR // snallie
/*
* 141~142行定义了Linux内核的默认下载地址（串口的文件默认下载地址也是这个地址）
*/
143
144 /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
145 /* it to wrap 100 times (total 1562500) to get 1 sec. */
146 #define CFG_HZ 1562500
147
148 /* valid baudrates */
149 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
150
151 #ifndef __ASSEMBLY__
152 /*-----------------------------------------------------------------------
153 * Board specific extension for bd_info
154 *
155 * This structure is embedded in the global bd_info (bd_t) structure
156 * and can be used by the board specific code (eg board/...)
157 */
158
159 struct bd_info_ext
160 {
161 /* helper variable for board environment handling
162 *
163 * env_crc_valid == 0 => uninitialised
164 * env_crc_valid > 0 => environment crc in flash is valid
165 * env_crc_valid < 0 => environment crc in flash is invalid
166 */
167 int env_crc_valid;
168 };
169 #endif
170
171 /*-----------------------------------------------------------------------
172 * Stack sizes
173 *
174 * The stack sizes are set up in start.S using the settings below
175 */
176 #define CONFIG_STACKSIZE (128*1024) /* regular stack */
177 #ifdef CONFIG_USE_IRQ
178 #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
179 #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
180 #endif
181
182 /*-----------------------------------------------------------------------
183 * Physical Memory Map
184 */
185 #if defined(CONFIG_SMDK2410) // snallie
186 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
187 #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
188 #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
189
190 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
191 #define PHYS_FLASH_SIZE 0x00100000 /* 1 MB */
192
193 #define CFG_FLASH_BASE PHYS_FLASH_1
194 #endif // snallie
195
196 #if defined(CONFIG_MINI2440) // snallie
197 #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
198 #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
199 #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
200
201 #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
202 #define PHYS_FLASH_SIZE 0x00200000 /* 2 MB */
203
204 #define CFG_FLASH_BASE PHYS_FLASH_1
205 #endif // snallie
/*
* 196~205行定义了RAM的起始地址及RAM的大小以及FLASH的起始地址及FLASH的大小。
*/
206 /*-----------------------------------------------------------------------
207 * FLASH and environment organization
208 */
209 #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
210 #define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
211
212 /* timeout values are in ticks */
213 #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
214 #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
215
216 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* Addr of Environment Sector */
217 #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
218
219 // snallie
220 /*-----------------------------------------------------------------------
221 * KERNEL configs
222 */
223 #define CONFIG_KERNEL_OFFSET_ON_NAND 0x50000
224 #define CONFIG_KERNEL_SIZE 0x200000
225 // snallie
/*
* 223~224行定义了Linux内核文件在NANDFLASH上的起始地址以及内核文件的大小。
*/
226 #endif /* __CONFIG_H */
///////////
修改board/mini2440/Makefile,将 boot_init.c 编译到映像模块中，如下：
1 #
2 # (C) Copyright 2000, 2001, 2002
3 # Wolfgang Denk, DENX Software Engineering, [email protected].
4 #
5 # See file CREDITS for list of people who contributed to this
6 # project.
7 #
8 # This program is free software; you can redistribute it and/or
9 # modify it under the terms of the GNU General Public License as
10 # published by the Free Software Foundation; either version 2 of
11 # the License, or (at your option) any later version.
12 #
13 # This program is distributed in the hope that it will be useful,
14 # but WITHOUT ANY WARRANTY; without even the implied warranty of
15 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 # GNU General Public License for more details.
17 #
18 # You should have received a copy of the GNU General Public License
19 # along with this program; if not, write to the Free Software
20 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 # MA 02111-1307 USA
22 #
23
24 include $(TOPDIR)/config.mk
25
26 LIB = lib$(BOARD).a
27
28 # OBJS := smdk2410.o flash.o env.o # snallie, 2011-05-24_193056_Tue
29 OBJS := mini2440.o flash.o env.o boot_init.o # snallie, 2011-05-24_193056_Tue
# 第29行追加boot_init.o ，使得boot_init.c被编译到映像模块中
30 SOBJS := memsetup.o
31
32 $(LIB): $(OBJS) $(SOBJS)
33 $(AR) crv $@ $^
34
35 clean:
36 rm -f $(SOBJS) $(OBJS)
37
38 distclean: clean
39 rm -f $(LIB) core *.bak .depend
40
41 #########################################################################
42
43 .depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
44 $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
45
46 -include .depend
47
48 #########################################################################
/////////////
引入网络芯片dm9000的驱动程序dm9000x.c和dm9000x.h到 drivers 目录下，（来源于u-boot-1.1.2）
做少许修改：
drivers/dm9000x.c
1 /*
2 dm9000.c: Version 1.2 12/15/2003
3
4 A Davicom DM9000 ISA NIC fast Ethernet driver for Linux.
5 Copyright (C) 1997 Sten Wang
6
7 This program is free software; you can redistribute it and/or
8 modify it under the terms of the GNU General Public License
9 as published by the Free Software Foundation; either version 2
10 of the License, or (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 (C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
18
19 V0.11 06/20/2001 REG_0A bit3=1, default enable BP with DA match
20 06/22/2001 Support DM9801 progrmming
21 E3: R25 = ((R24 + NF) & 0x00ff) | 0xf000
22 E4: R25 = ((R24 + NF) & 0x00ff) | 0xc200
23 R17 = (R17 & 0xfff0) | NF + 3
24 E5: R25 = ((R24 + NF - 3) & 0x00ff) | 0xc200
25 R17 = (R17 & 0xfff0) | NF
26
27 v1.00 modify by simon 2001.9.5
28 change for kernel 2.4.x
29
30 v1.1 11/09/2001 fix force mode bug
31
32 v1.2 03/18/2003 Weilun Huang
33 Fixed phy reset.
34 Added tx/rx 32 bit mode.
35 Cleaned up for kernel merge.
36
37 --------------------------------------
38
39 12/15/2003 Initial port to u-boot by Sascha Hauer
40
41 TODO: Homerun NIC and longrun NIC are not functional, only internal at the
42 moment.
43 */
44
45 //#include
46 #include
/*
* 45~46修改所包含的头文件
*/
47 #include
48 #include
49 #include
50
51 #ifdef CONFIG_DRIVER_DM9000
52
53 #include "dm9000x.h"
54
55 /* Board/System/Debug information/definition ---------------- */
56
57 #define DM9801_NOISE_FLOOR 0x08
58 #define DM9802_NOISE_FLOOR 0x05
59
60 /* #define CONFIG_DM9000_DEBUG */
61
62 #ifdef CONFIG_DM9000_DEBUG
63 #define DM9000_DBG(fmt,args...) printf(fmt ,##args)
64 #else /* */
65 #define DM9000_DBG(fmt,args...)
66 #endif /* */
67 enum DM9000_PHY_mode { DM9000_10MHD = 0, DM9000_100MHD =
68 1, DM9000_10MFD = 4, DM9000_100MFD = 5, DM9000_AUTO =
69 8, DM9000_1M_HPNA = 0x10
70 };
71 enum DM9000_NIC_TYPE { FASTETHER_NIC = 0, HOMERUN_NIC = 1, LONGRUN_NIC = 2
72 };
73
74 /* Structure/enum declaration ------------------------------- */
75 typedef struct board_info {
76 u32 runt_length_counter; /* counter: RX length < 64byte */
77 u32 long_length_counter; /* counter: RX length > 1514byte */
78 u32 reset_counter; /* counter: RESET */
79 u32 reset_tx_timeout; /* RESET caused by TX Timeout */
80 u32 reset_rx_status; /* RESET caused by RX Statsus wrong */
81 u16 tx_pkt_cnt;
82 u16 queue_start_addr;
83 u16 dbug_cnt;
84 u8 phy_addr;
85 u8 device_wait_reset; /* device state */
86 u8 nic_type; /* NIC type */
87 unsigned char srom[128];
88 } board_info_t;
89 board_info_t dmfe_info;
90
91 /* For module input parameter */
92 static int media_mode = DM9000_AUTO;
93 static u8 nfloor = 0;
94
95 /* function declaration ------------------------------------- */
96 int eth_init(bd_t * bd);
97 int eth_send(volatile void *, int);
98 int eth_rx(void);
99 void eth_halt(void);
100 static int dm9000_probe(void);
101 static u16 phy_read(int);
102 static void phy_write(int, u16);
103 static u16 read_srom_word(int);
104 static u8 DM9000_ior(int);
105 static void DM9000_iow(int reg, u8 value);
106
107 /* DM9000 network board routine ---------------------------- */
108
109 #define DM9000_outb(d,r) ( *(volatile u8 *)r = d )
110 #define DM9000_outw(d,r) ( *(volatile u16 *)r = d )
111 #define DM9000_outl(d,r) ( *(volatile u32 *)r = d )
112 #define DM9000_inb(r) (*(volatile u8 *)r)
113 #define DM9000_inw(r) (*(volatile u16 *)r)
114 #define DM9000_inl(r) (*(volatile u32 *)r)
115
116 #ifdef CONFIG_DM9000_DEBUG
117 static void
118 dump_regs(void)
119 {
120 DM9000_DBG("/n");
121 DM9000_DBG("NCR (0x00): %02x/n", DM9000_ior(0));
122 DM9000_DBG("NSR (0x01): %02x/n", DM9000_ior(1));
123 DM9000_DBG("TCR (0x02): %02x/n", DM9000_ior(2));
124 DM9000_DBG("TSRI (0x03): %02x/n", DM9000_ior(3));
125 DM9000_DBG("TSRII (0x04): %02x/n", DM9000_ior(4));
126 DM9000_DBG("RCR (0x05): %02x/n", DM9000_ior(5));
127 DM9000_DBG("RSR (0x06): %02x/n", DM9000_ior(6));
128 DM9000_DBG("ISR (0xFE): %02x/n", DM9000_ior(DM9000_ISR)); /* snallie */
/*
* 128修改DM9000的ISR寄存器的偏移量DM9000_ISR定义在dm9000x.h头文件中
*/
129 DM9000_DBG("/n");
130 }
131 #endif /* */
132
133 /*
134 Search DM9000 board, allocate space and register it
135 */
136 int
137 dm9000_probe(void)
138 {
139 u32 id_val;
140 id_val = DM9000_ior(DM9000_VIDL);
141 id_val |= DM9000_ior(DM9000_VIDH) << 8;
142 id_val |= DM9000_ior(DM9000_PIDL) << 16;
143 id_val |= DM9000_ior(DM9000_PIDH) << 24;
144 if (id_val == DM9000_ID) {
145 printf("dm9000 i/o: 0x%x, id: 0x%08lx /n", CONFIG_DM9000_BASE,
146 id_val);
147 return 0;
148 } else {
149 printf("dm9000 not found at 0x%08x id: 0x%08lx/n",
150 CONFIG_DM9000_BASE, id_val);
151 return -1;
152 }
153 }
154
155 /* Set PHY operationg mode
156 */
157 static void
158 set_PHY_mode(void)
159 {
160 u16 phy_reg4 = 0x01e1, phy_reg0 = 0x1000;
161 if (!(media_mode & DM9000_AUTO)) {
162 switch (media_mode) {
163 case DM9000_10MHD:
164 phy_reg4 = 0x21;
165 phy_reg0 = 0x0000;
166 break;
167 case DM9000_10MFD:
168 phy_reg4 = 0x41;
169 phy_reg0 = 0x1100;
170 break;
171 case DM9000_100MHD:
172 phy_reg4 = 0x81;
173 phy_reg0 = 0x2000;
174 break;
175 case DM9000_100MFD:
176 phy_reg4 = 0x101;
177 phy_reg0 = 0x3100;
178 break;
179 }
180 phy_write(4, phy_reg4); /* Set PHY media mode */
181 phy_write(0, phy_reg0); /* Tmp */
182 }
183 DM9000_iow(DM9000_GPCR, 0x01); /* Let GPIO0 output */
184 DM9000_iow(DM9000_GPR, 0x00); /* Enable PHY */
185 }
186
187 /*
188 Init HomeRun DM9801
189 */
190 static void
191 program_dm9801(u16 HPNA_rev)
192 {
193 __u16 reg16, reg17, reg24, reg25;
194 if (!nfloor)
195 nfloor = DM9801_NOISE_FLOOR;
196 reg16 = phy_read(16);
197 reg17 = phy_read(17);
198 reg24 = phy_read(24);
199 reg25 = phy_read(25);
200 switch (HPNA_rev) {
201 case 0xb900: /* DM9801 E3 */
202 reg16 |= 0x1000;
203 reg25 = ((reg24 + nfloor) & 0x00ff) | 0xf000;
204 break;
205 case 0xb901: /* DM9801 E4 */
206 reg25 = ((reg24 + nfloor) & 0x00ff) | 0xc200;
207 reg17 = (reg17 & 0xfff0) + nfloor + 3;
208 break;
209 case 0xb902: /* DM9801 E5 */
210 case 0xb903: /* DM9801 E6 */
211 default:
212 reg16 |= 0x1000;
213 reg25 = ((reg24 + nfloor - 3) & 0x00ff) | 0xc200;
214 reg17 = (reg17 & 0xfff0) + nfloor;
215 }
216 phy_write(16, reg16);
217 phy_write(17, reg17);
218 phy_write(25, reg25);
219 }
220
221 /*
222 Init LongRun DM9802
223 */
224 static void
225 program_dm9802(void)
226 {
227 __u16 reg25;
228 if (!nfloor)
229 nfloor = DM9802_NOISE_FLOOR;
230 reg25 = phy_read(25);
231 reg25 = (reg25 & 0xff00) + nfloor;
232 phy_write(25, reg25);
233 }
234
235 /* Identify NIC type
236 */
237 static void
238 identify_nic(void)
239 {
240 struct board_info *db = &dmfe_info; /* Point a board information structure */
241 u16 phy_reg3;
242 DM9000_iow(DM9000_NCR, NCR_EXT_PHY);
243 phy_reg3 = phy_read(3);
244 switch (phy_reg3 & 0xfff0) {
245 case 0xb900:
246 if (phy_read(31) == 0x4404) {
247 db->nic_type = HOMERUN_NIC;
248 program_dm9801(phy_reg3);
249 DM9000_DBG("found homerun NIC/n");
250 } else {
251 db->nic_type = LONGRUN_NIC;
252 DM9000_DBG("found longrun NIC/n");
253 program_dm9802();
254 }
255 break;
256 default:
257 db->nic_type = FASTETHER_NIC;
258 break;
259 }
260 DM9000_iow(DM9000_NCR, 0);
261 }
262
263 /* General Purpose dm9000 reset routine */
264 static void
265 dm9000_reset(void)
266 {
267 DM9000_DBG("resetting/n");
268 DM9000_iow(DM9000_NCR, NCR_RST);
269 udelay(1000); /* delay 1ms */
270 }
271
272 /* Initilize dm9000 board
273 */
274 int
275 eth_init(bd_t * bd)
276 {
277 int i, oft, lnk;
278 DM9000_DBG("eth_init()/n");
279
280 /* RESET device */
281 dm9000_reset();
282 dm9000_probe();
283
284 /* NIC Type: FASTETHER, HOMERUN, LONGRUN */
285 identify_nic();
286
287 /* GPIO0 on pre-activate PHY */
288 DM9000_iow(DM9000_GPR, 0x00); /*REG_1F bit0 activate phyxcer */
289
290 /* Set PHY */
291 set_PHY_mode();
292
293 /* Program operating register */
294 DM9000_iow(DM9000_NCR, 0x0); /* only intern phy supported by now */
295 DM9000_iow(DM9000_TCR, 0); /* TX Polling clear */
296 DM9000_iow(DM9000_BPTR, 0x3f); /* Less 3Kb, 200us */
297 DM9000_iow(DM9000_FCTR, FCTR_HWOT(3) | FCTR_LWOT(8)); /* Flow Control : High/Low Water */
298 DM9000_iow(DM9000_FCR, 0x0); /* SH FIXME: This looks strange! Flow Control */
299 DM9000_iow(DM9000_SMCR, 0); /* Special Mode */
300 DM9000_iow(DM9000_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); /* clear TX status */
301 DM9000_iow(DM9000_ISR, 0x0f); /* Clear interrupt status */
302
303 /* Set Node address */
304 // snalie
305 #if 1
306 for (i = 0; i < 6; i++)
307 printf("%08x ", read_srom_word(i));
308 printf("/n");
309 #endif
310 #ifndef CONFIG_ETHADDR
311 for (i = 0; i < 6; i++)
312 ((u16 *) bd->bi_enetaddr)[i] = read_srom_word(i);
313 #endif
/*
* 305~313加入调试输出
*/
314 // snallie
315 printf("MAC: %02x:%02x:%02x:%02x:%02x:%02x/n", bd->bi_enetaddr[0],
316 bd->bi_enetaddr[1], bd->bi_enetaddr[2], bd->bi_enetaddr[3],
317 bd->bi_enetaddr[4], bd->bi_enetaddr[5]);
318 for (i = 0, oft = 0x10; i < 6; i++, oft++)
319 DM9000_iow(oft, bd->bi_enetaddr[i]);
320 for (i = 0, oft = 0x16; i < 8; i++, oft++)
321 DM9000_iow(oft, 0xff);
322
323 /* read back mac, just to be sure */
324 for (i = 0, oft = 0x10; i < 6; i++, oft++)
325 DM9000_DBG("%02x:", DM9000_ior(oft));
326 DM9000_DBG("/n");
327
328 /* Activate DM9000 */
329 DM9000_iow(DM9000_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); /* RX enable */
330 DM9000_iow(DM9000_IMR, IMR_PAR); /* Enable TX/RX interrupt mask */
331 i = 0;
332 while (!(phy_read(1) & 0x20)) { /* autonegation complete bit */
333 udelay(1000);
334 i++;
335 if (i == 10000) {
336 printf("could not establish link/n");
337 return 0;
338 }
339 }
340
341 /* see what we've got */
342 lnk = phy_read(17) >> 12;
343 printf("operating at ");
344 switch (lnk) {
345 case 1:
346 printf("10M half duplex ");
347 break;
348 case 2:
349 printf("10M full duplex ");
350 break;
351 case 4:
352 printf("100M half duplex ");
353 break;
354 case 8:
355 printf("100M full duplex ");
356 break;
357 default:
358 printf("unknown: %d ", lnk);
359 break;
360 }
361 printf("mode/n");
362 return 0;
363 }
364
365 /*
366 Hardware start transmission.
367 Send a packet to media from the upper layer.
368 */
369 int
370 eth_send(volatile void *packet, int length)
371 {
372 char *data_ptr;
373 u32 tmplen, i;
374 int tmo;
375 DM9000_DBG("eth_send: length: %d/n", length);
376 for (i = 0; i < length; i++) {
377 if (i % 8 == 0)
378 DM9000_DBG("/nSend: 02x: ", i);
379 DM9000_DBG("%02x ", ((unsigned char *) packet)[i]);
380 } DM9000_DBG("/n");
381
382 /* Move data to DM9000 TX RAM */
383 data_ptr = (char *) packet;
384 DM9000_outb(DM9000_MWCMD, DM9000_IO);
385
386 #ifdef CONFIG_DM9000_USE_8BIT
387 /* Byte mode */
388 for (i = 0; i < length; i++)
389 DM9000_outb((data_ptr[i] & 0xff), DM9000_DATA);
390
391 #endif /* */
392 #ifdef CONFIG_DM9000_USE_16BIT
393 tmplen = (length + 1) / 2;
394 for (i = 0; i < tmplen; i++)
395 DM9000_outw(((u16 *) data_ptr)[i], DM9000_DATA);
396
397 #endif /* */
398 #ifdef CONFIG_DM9000_USE_32BIT
399 tmplen = (length + 3) / 4;
400 for (i = 0; i < tmplen; i++)
401 DM9000_outl(((u32 *) data_ptr)[i], DM9000_DATA);
402
403 #endif /* */
404
405 /* Set TX length to DM9000 */
406 DM9000_iow(DM9000_TXPLL, length & 0xff);
407 DM9000_iow(DM9000_TXPLH, (length >> 8) & 0xff);
408
409 /* Issue TX polling command */
410 DM9000_iow(DM9000_TCR, TCR_TXREQ); /* Cleared after TX complete */
411
412 /* wait for end of transmission */
413 tmo = get_timer(0) + 5 * CFG_HZ;
414 while (DM9000_ior(DM9000_TCR) & TCR_TXREQ) {
415 if (get_timer(0) >= tmo) {
416 printf("transmission timeout/n");
417 break;
418 }
419 }
420 DM9000_DBG("transmit done/n/n");
421 return 0;
422 }
423
424 /*
425 Stop the interface.
426 The interface is stopped when it is brought.
427 */
428 void
429 eth_halt(void)
430 {
431 DM9000_DBG("eth_halt/n");
432
433 /* RESET devie */
434 phy_write(0, 0x8000); /* PHY RESET */
435 DM9000_iow(DM9000_GPR, 0x01); /* Power-Down PHY */
436 DM9000_iow(DM9000_IMR, 0x80); /* Disable all interrupt */
437 DM9000_iow(DM9000_RCR, 0x00); /* Disable RX */
438 }
439
440 /*
441 Received a packet and pass to upper layer
442 */
443 int
444 eth_rx(void)
445 {
446 u8 rxbyte, *rdptr = (u8 *) NetRxPackets[0];
447 u16 RxStatus, RxLen = 0;
448 u32 tmplen, i;
449
450 /* Check packet ready or not */
451 DM9000_ior(DM9000_MRCMDX); /* Dummy read */
452 rxbyte = DM9000_inb(DM9000_DATA); /* Got most updated data */
453 if (rxbyte == 0)
454 return 0;
455
456 /* Status check: this byte must be 0 or 1 */
457 if (rxbyte > 1) {
458 DM9000_iow(DM9000_RCR, 0x00); /* Stop Device */
459 DM9000_iow(DM9000_ISR, 0x80); /* Stop INT request */
460 DM9000_DBG("rx status check: %d/n", rxbyte);
461 }
462 DM9000_DBG("receiving packet/n");
463
464 /* A packet ready now & Get status/length */
465 DM9000_outb(DM9000_MRCMD, DM9000_IO);
466
467 #ifdef CONFIG_DM9000_USE_8BIT
468 RxStatus = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
469 RxLen = DM9000_inb(DM9000_DATA) + (DM9000_inb(DM9000_DATA) << 8);
470
471 #endif /* */
472 #ifdef CONFIG_DM9000_USE_16BIT
473 RxStatus = DM9000_inw(DM9000_DATA);
474 RxLen = DM9000_inw(DM9000_DATA);
475
476 #endif /* */
477 #ifdef CONFIG_DM9000_USE_32BIT
478 tmpdata = DM9000_inl(DM9000_DATA);
479 RxStatus = tmpdata;
480 RxLen = tmpdata >> 16;
481
482 #endif /* */
483 DM9000_DBG("rx status: 0x%04x rx len: %d/n", RxStatus, RxLen);
484
485 /* Move data from DM9000 */
486 /* Read received packet from RX SRAM */
487 #ifdef CONFIG_DM9000_USE_8BIT
488 for (i = 0; i < RxLen; i++)
489 rdptr[i] = DM9000_inb(DM9000_DATA);
490
491 #endif /* */
492 #ifdef CONFIG_DM9000_USE_16BIT
493 tmplen = (RxLen + 1) / 2;
494 for (i = 0; i < tmplen; i++)
495 ((u16 *) rdptr)[i] = DM9000_inw(DM9000_DATA);
496
497 #endif /* */
498 #ifdef CONFIG_DM9000_USE_32BIT
499 tmplen = (RxLen + 3) / 4;
500 for (i = 0; i < tmplen; i++)
501 ((u32 *) rdptr)[i] = DM9000_inl(DM9000_DATA);
502
503 #endif /* */
504 if ((RxStatus & 0xbf00) || (RxLen < 0x40)
505 || (RxLen > DM9000_PKT_MAX)) {
506 if (RxStatus & 0x100) {
507 printf("rx fifo error/n");
508 }
509 if (RxStatus & 0x200) {
510 printf("rx crc error/n");
511 }
512 if (RxStatus & 0x8000) {
513 printf("rx length error/n");
514 }
515 if (RxLen > DM9000_PKT_MAX) {
516 printf("rx length too big/n");
517 dm9000_reset();
518 }
519 } else {
520
521 /* Pass to upper layer */
522 DM9000_DBG("passing packet to upper layer/n");
523 NetReceive(NetRxPackets[0], RxLen);
524 return RxLen;
525 }
526 return 0;
527 }
528
529 /*
530 Read a word data from SROM
531 */
532 static u16
533 read_srom_word(int offset)
534 {
535 DM9000_iow(DM9000_EPAR, offset);
536 DM9000_iow(DM9000_EPCR, 0x4);
537 udelay(200);
538 DM9000_iow(DM9000_EPCR, 0x0);
539 return (DM9000_ior(DM9000_EPDRL) + (DM9000_ior(DM9000_EPDRH) << 8));
540 }
541
542 /*
543 Read a byte from I/O port
544 */
545 static u8
546 DM9000_ior(int reg)
547 {
548 DM9000_outb(reg, DM9000_IO);
549 return DM9000_inb(DM9000_DATA);
550 }
551
552 /*
553 Write a byte to I/O port
554 */
555 static void
556 DM9000_iow(int reg, u8 value)
557 {
558 DM9000_outb(reg, DM9000_IO);
559 DM9000_outb(value, DM9000_DATA);
560 }
561
562 /*
563 Read a word from phyxcer
564 */
565 static u16
566 phy_read(int reg)
567 {
568 u16 val;
569
570 /* Fill the phyxcer register into REG_0C */
571 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
572 DM9000_iow(DM9000_EPCR, 0xc); /* Issue phyxcer read command */
573 udelay(100); /* Wait read complete */
574 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer read command */
575 val = (DM9000_ior(DM9000_EPDRH) << 8) | DM9000_ior(DM9000_EPDRL);
576
577 /* The read data keeps on REG_0D & REG_0E */
578 DM9000_DBG("phy_read(%d): %d/n", reg, val);
579 return val;
580 }
581
582 /*
583 Write a word to phyxcer
584 */
585 static void
586 phy_write(int reg, u16 value)
587 {
588
589 /* Fill the phyxcer register into REG_0C */
590 DM9000_iow(DM9000_EPAR, DM9000_PHY | reg);
591
592 /* Fill the written data into REG_0D & REG_0E */
593 DM9000_iow(DM9000_EPDRL, (value & 0xff));
594 DM9000_iow(DM9000_EPDRH, ((value >> 8) & 0xff));
595 DM9000_iow(DM9000_EPCR, 0xa); /* Issue phyxcer write command */
596 udelay(500); /* Wait write complete */
597 DM9000_iow(DM9000_EPCR, 0x0); /* Clear phyxcer write command */
598 DM9000_DBG("phy_write(reg:%d, value:%d)/n", reg, value);
599 }
600 #endif /* CONFIG_DRIVER_DM9000 */
////////////
引入和dm9000x.c相关的头文件dm9000x.h，如下，无需任何修改
drivers/dm9000x.h
1 /*
2 * dm9000 Ethernet
3 */
4
5 #ifdef CONFIG_DRIVER_DM9000
6
7 #define DM9000_ID 0x90000A46
8 #define DM9000_PKT_MAX 1536 /* Received packet max size */
9 #define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
10
11 /* although the registers are 16 bit, they are 32-bit aligned.
12 */
13
14 #define DM9000_NCR 0x00
15 #define DM9000_NSR 0x01
16 #define DM9000_TCR 0x02
17 #define DM9000_TSR1 0x03
18 #define DM9000_TSR2 0x04
19 #define DM9000_RCR 0x05
20 #define DM9000_RSR 0x06
21 #define DM9000_ROCR 0x07
22 #define DM9000_BPTR 0x08
23 #define DM9000_FCTR 0x09
24 #define DM9000_FCR 0x0A
25 #define DM9000_EPCR 0x0B
26 #define DM9000_EPAR 0x0C
27 #define DM9000_EPDRL 0x0D
28 #define DM9000_EPDRH 0x0E
29 #define DM9000_WCR 0x0F
30
31 #define DM9000_PAR 0x10
32 #define DM9000_MAR 0x16
33
34 #define DM9000_GPCR 0x1e
35 #define DM9000_GPR 0x1f
36 #define DM9000_TRPAL 0x22
37 #define DM9000_TRPAH 0x23
38 #define DM9000_RWPAL 0x24
39 #define DM9000_RWPAH 0x25
40
41 #define DM9000_VIDL 0x28
42 #define DM9000_VIDH 0x29
43 #define DM9000_PIDL 0x2A
44 #define DM9000_PIDH 0x2B
45
46 #define DM9000_CHIPR 0x2C
47 #define DM9000_SMCR 0x2F
48
49 #define DM9000_PHY 0x40 /* PHY address 0x01 */
50
51 #define DM9000_MRCMDX 0xF0
52 #define DM9000_MRCMD 0xF2
53 #define DM9000_MRRL 0xF4
54 #define DM9000_MRRH 0xF5
55 #define DM9000_MWCMDX 0xF6
56 #define DM9000_MWCMD 0xF8
57 #define DM9000_MWRL 0xFA
58 #define DM9000_MWRH 0xFB
59 #define DM9000_TXPLL 0xFC
60 #define DM9000_TXPLH 0xFD
61 #define DM9000_ISR 0xFE
62 #define DM9000_IMR 0xFF
63
64 #define NCR_EXT_PHY (1<<7)
65 #define NCR_WAKEEN (1<<6)
66 #define NCR_FCOL (1<<4)
67 #define NCR_FDX (1<<3)
68 #define NCR_LBK (3<<1)
69 #define NCR_RST (1<<0)
70
71 #define NSR_SPEED (1<<7)
72 #define NSR_LINKST (1<<6)
73 #define NSR_WAKEST (1<<5)
74 #define NSR_TX2END (1<<3)
75 #define NSR_TX1END (1<<2)
76 #define NSR_RXOV (1<<1)
77
78 #define TCR_TJDIS (1<<6)
79 #define TCR_EXCECM (1<<5)
80 #define TCR_PAD_DIS2 (1<<4)
81 #define TCR_CRC_DIS2 (1<<3)
82 #define TCR_PAD_DIS1 (1<<2)
83 #define TCR_CRC_DIS1 (1<<1)
84 #define TCR_TXREQ (1<<0)
85
86 #define TSR_TJTO (1<<7)
87 #define TSR_LC (1<<6)
88 #define TSR_NC (1<<5)
89 #define TSR_LCOL (1<<4)
90 #define TSR_COL (1<<3)
91 #define TSR_EC (1<<2)
92
93 #define RCR_WTDIS (1<<6)
94 #define RCR_DIS_LONG (1<<5)
95 #define RCR_DIS_CRC (1<<4)
96 #define RCR_ALL (1<<3)
97 #define RCR_RUNT (1<<2)
98 #define RCR_PRMSC (1<<1)
99 #define RCR_RXEN (1<<0)
100
101 #define RSR_RF (1<<7)
102 #define RSR_MF (1<<6)
103 #define RSR_LCS (1<<5)
104 #define RSR_RWTO (1<<4)
105 #define RSR_PLE (1<<3)
106 #define RSR_AE (1<<2)
107 #define RSR_CE (1<<1)
108 #define RSR_FOE (1<<0)
109
110 #define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
111 #define FCTR_LWOT(ot) ( ot & 0xf )
112
113 #define IMR_PAR (1<<7)
114 #define IMR_ROOM (1<<3)
115 #define IMR_ROM (1<<2)
116 #define IMR_PTM (1<<1)
117 #define IMR_PRM (1<<0)
118
119 #endif
//////////
修改drivers/Makefile，加入dm9000x.c的编译，如下
1 #
2 # (C) Copyright 2002
3 # Sysgo Real-Time Solutions, GmbH
4 # Marius Groeger
5 #
6 # See file CREDITS for list of people who contributed to this
7 # project.
8 #
9 # This program is free software; you can redistribute it and/or
10 # modify it under the terms of the GNU General Public License as
11 # published by the Free Software Foundation; either version 2 of
12 # the License, or (at your option) any later version.
13 #
14 # This program is distributed in the hope that it will be useful,
15 # but WITHOUT ANY WARRANTY; without even the implied warranty of
16 # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 # GNU General Public License for more details.
18 #
19 # You should have received a copy of the GNU General Public License
20 # along with this program; if not, write to the Free Software
21 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 # MA 02111-1307 USA
23 #
24
25 include $(TOPDIR)/config.mk
26
27 LIB = libdrivers.a
28
29 OBJS = cs8900.o smc91111.o 3c589.o dm9000x.o
# 29行尾追加 dm9000x.o，使得dm9000x.c被编译进来
30
31 all: .depend $(START) $(LIB)
32
33 $(LIB): $(OBJS)
34 $(AR) crv $@ $(OBJS)
35
36 #########################################################################
37
38 .depend: Makefile $(START:.o=.S) $(OBJS:.o=.c)
39 $(CC) -M $(CFLAGS) $(START:.o=.S) $(OBJS:.o=.c) > $@
40
41 sinclude .depend
42
43 #########################################################################
////////////
编译测试：
[root@arm armboot-1.1.0]# make distclean ;make mini2440_config ; make all
通过编译，编译结果：
[root@armdev armboot-1.1.0]# ls -altr
-rwxr-xr-x 1 root root 234740 May 24 22:31 armboot.srec
-rw-r--r-- 1 root root 29063 May 24 22:31 armboot.map
-rw-r--r-- 1 root root 220086 May 24 22:31 armboot.hex
-rwxr-xr-x 1 root root 78224 May 24 22:31 armboot.bin
-rwxr-xr-x 1 root root 95823 May 24 22:31 armboot
将armboot.bin下载到0x31f00000地址处运行（串口参数：115200，n81），输出信息：(/* 中的的内容为加如的说明文字 */)
ARMboot 1.1.0 (May 24 2011 - 22:31:04)
ARMboot code: 31f00000 -> 31f16440
DRAM Configuration:
Bank #0: 30000000 64 MB
Flash: 2 MB
*** Using default environment
Hit any key to stop autoboot: 0
ARMboot@MINI2440 # help /* 看看ARMboot 1.1.0帮助信息，是不是和U-boot很相似:> */
go - start application at address 'addr'
run - run commands in an environment variable
bootm - boot application image from memory
bootp - boot image via network using BootP/TFTP protocol
tftpboot- boot image via network using TFTP protocol
and env variables ipaddr and serverip
rarpboot- boot image via network using RARP/TFTP protocol
bootd - boot default, i.e., run 'bootcmd'
loads - load S-Record file over serial line
loadb - load binary file over serial line (kermit mode)
autoscr - run script from memory
md - memory display
mm - memory modify (auto-incrementing)
nm - memory modify (constant address)
mw - memory write (fill)
cp - memory copy
cmp - memory compare
crc32 - checksum calculation
base - print or set address offset
printenv- print environment variables
setenv - set environment variables
saveenv - save environment variables to persistent storage
protect - enable or disable FLASH write protection
erase - erase FLASH memory
flinfo - print FLASH memory information
bdinfo - print Board Info structure
iminfo - print header information for application image
loop - infinite loop on address range
mtest - simple RAM test
icache - enable or disable instruction cache
dcache - enable or disable data cache
reset - Perform RESET of the CPU
echo - echo args to console
sleep - delay execution for some time
version - print monitor version
help - print online help
? - alias for 'help'
ARMboot@MINI2440 #
ARMboot@MINI2440 # loadb 30000000 /* 串口下载个文本文件看看，存放到RAM 的0x30000000地址处 */
## Ready for binary (kermit) download ...
## Start Addr = 0x30000000
ARMboot@MINI2440 # md 30000000 /* 看看0x30000000地址处的下载内容，应该和你的原始数据相同 */
30000000: 6f6f725b 72464074 646e6569 5241796c [root@FriendlyAR
30000010: 5d2f204d 73752023 2d312062 6e203a31 M /]# usb 1-1: n
30000020: 66207765 206c6c75 65657073 53552064 ew full speed US
30000030: 65642042 65636976 69737520 7320676e B device using s
30000040: 34326333 6f2d3031 20696368 20646e61 3c2410-ohci and
30000050: 72646461 20737365 750a0d32 31206273 address 2..usb 1
30000060: 203a312d 2077654e 20425355 69766564 -1: New USB devi
30000070: 66206563 646e756f 6469202c 646e6556 ce found, idVend
30000080: 353d726f 2c383434 50646920 75646f72 or=5448, idProdu
30000090: 303d7463 0d343030 6273750a 312d3120 ct=0004..usb 1-1
300000a0: 654e203a 53552077 65642042 65636976 : New USB device
300000b0: 72747320 73676e69 664d203a 2c343d72 strings: Mfr=4,
300000c0: 6f725020 74637564 202c333d 69726553 Product=3, Seri
300000d0: 754e6c61 7265626d 0a0d323d 20627375 alNumber=2..usb
300000e0: 3a312d31 6f725020 74637564 5355203a 1-1: Product: US
300000f0: 79654b42 73750a0d 2d312062 4d203a31 BKey..usb 1-1: M
ARMboot@MINI2440 # /* 键入回车继续查看 */
30000100: 66756e61 75746361 3a726572 42535520 anufacturer: USB
30000110: 0d79654b 6273750a 312d3120 6553203a Key..usb 1-1: Se
30000120: 6c616972 626d754e 203a7265 750a0d3f rialNumber: ?..u
30000130: 31206273 203a312d 666e6f63 72756769 sb 1-1: configur
30000140: 6f697461 3123206e 6f686320 206e6573 ation #1 chosen
30000150: 6d6f7266 63203120 63696f68 730a0d65 from 1 choice..s
30000160: 30697363 53203a20 20495343 6c756d65 csi0 : SCSI emul
30000170: 6f697461 6f66206e 53552072 614d2042 ation for USB Ma
30000180: 53207373 61726f74 64206567 63697665 ss Storage devic
30000190: 0a0d7365 69736373 61637320 49203a6e es..scsi scan: I
300001a0: 4955514e 72205952 6c757365 6f742074 NQUIRY result to
300001b0: 6873206f 2074726f 2c293528 69737520 o short (5), usi
300001c0: 3320676e 730a0d36 20697363 3a303a30 ng 36..scsi 0:0:
300001d0: 3a303a30 2d444320 204d4f52 20202020 0:0: CD-ROM
300001e0: 20202020 20202020 20202020 20202020
300001f0: 4f524443 2020204d 20202020 20202020 CDROM
ARMboot@MINI2440 # printenv /* 看看环境变量 */
bootargs=noinitrd root=/dev/mtdblock2 init=/linuxrc console=ttySAC0,115200n8
bootcmd=nboot
bootdelay=3
baudrate=115200
ethaddr=08:00:3e:26:0a:5b
ipaddr=192.168.2.2
serverip=192.168.2.1
netmask=255.255.255.0
bootfile="uImage110_2440"
loadaddr=0x30008000
Environment size: 253/65532 bytes
ARMboot@MINI2440 # bdinfo /* 看看板子的配置信息 */
enetaddr = 08:00:3E:26:0A:5B
ip_addr = 192.168.2.2
baudrate = 115200 bps
arch_number = 193
env_t = 31F36448
boot_params = 30000100
DRAM:00.start = 30000000
DRAM:00.size = 04000000
ARMboot@MINI2440 # tftp 0x30008000 uImage110_2440 /* 通过tftp下载个uImage看看，前提是要设定网络环境，你的tftp服务器应没有防火墙，所下载的文件可以被tftp服务器读到 */
dm9000 i/o: 0x20000000, id: 0x90000a46
00008000 00000000 00000000 00000000 00000000 00000000
MAC: 08:00:3e:26:0a:5b
could not establish link
ARP broadcast 1
checksum bad
checksum bad
eth addr: 00:0c:29:9d:30:4b
TFTP from server 192.168.2.1; our IP address is 192.168.2.2
Filename 'uImage110_2440'.
Load address: 0x30008000
Loading: #######################################################################
################################################################################
################################################################################
################################################################################
################################################################################
#####
done
Bytes transferred = 2022412 (1edc0c hex)
ARMboot@MINI2440 # bootm /* 下载的uImage可以通过bootm命令来引导这个内核映像，uImage和zImage内核有区别（多了64字节的头），bootm只能引导uImage */
/////////////
下一加入nboot命令可以从nand引导zImage
修改 board/mini2440/mini2440.c 如下：
1 /*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH
4 * Marius Groeger
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG,
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28 #include "armboot.h"
29 #if defined(CONFIG_SMDK2410) // snallie
30 #include "s3c2410.h"
31 #endif
32
33 #if defined(CONFIG_MINI2440) // snallie
34 #include "s3c2440.h"
35 #endif
/*
* 33~35包含s3c2440.h
*/
36
37 /* ------------------------------------------------------------------------- */
38
39 #define FCLK_SPEED 1
40
41 #if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */
42 #define M_MDIV 0xC3
43 #define M_PDIV 0x4
44 #define M_SDIV 0x1
45 #elif FCLK_SPEED==1 /* Fout = 202.8MHz */
46 #define M_MDIV 0xA1
47 #define M_PDIV 0x3
48 #define M_SDIV 0x1
49 #endif
50
51 #define USB_CLOCK 1
52
53 #if USB_CLOCK==0
54 #define U_M_MDIV 0xA1
55 #define U_M_PDIV 0x3
56 #define U_M_SDIV 0x1
57 #elif USB_CLOCK==1
58 #define U_M_MDIV 0x48
59 #define U_M_PDIV 0x3
60 #define U_M_SDIV 0x2
61 #endif
62
63 static inline
64 void delay(unsigned long loops)
65 {
66 __asm__ volatile (
67 "1:/n"
68 "subs %0, %1, #1/n"
69 "bne 1b"
70 : "=r" (loops) : "0" (loops));
71 }
72
73 /*
74 * Miscellaneous platform dependent initialisations
75 */
76
77 int board_init(bd_t *bd)
78 {
79 #if defined(CONFIG_SMDK2410) // snallie
80 /* to reduce PLL lock time, adjust the LOCKTIME register */
81 rLOCKTIME = 0xFFFFFF;
82
83 /* configure MPLL */
84 rMPLLCON = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
85
86 /* some delay between MPLL and UPLL */
87 delay(4000);
88
89 /* configure UPLL */
90 rUPLLCON = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
91
92 /* some delay between MPLL and UPLL */
93 delay(8000);
94 #endif // snallie
/*
* 79~94 保留原有的SMDK2410代码
*/
95
96 #if defined(CONFIG_MINI2440) // snallie
97 /* to reduce PLL lock time, adjust the LOCKTIME register */
98 rLOCKTIME = 0xFFFFFF;
99
100 /* configure MPLL */
101 rMPLLCON = ((0x7f<<12)|(0x02<<4)|(0x01)); //((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV);
102
103 /* some delay between MPLL and UPLL */
104 delay(4000);
105
106 /* configure UPLL */
107 rUPLLCON = ((0x38<<12)|(0x02<<4)|(0x02)); //((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV);
108
109 /* some delay between MPLL and UPLL */
110 delay(8000);
111 #endif // snallie
/*
* 96~111 配置时钟参数 400M,100M,50M (1:4:8)
*/
112
113 /* set up the I/O ports */
114 rGPACON = 0x007FFFFF;
115 #if defined(CONFIG_MINI2440)
116 //rGPBCON = 0x00295551; // snallie , Sun Feb 20 15:36:57 CST 2011
117 rGPBCON = 0x15400; // GPB5~8 output(LED1~4),GPB0=0=input(buzzer off),(GPB0=0b10=TOUT0)
118 #else
119 rGPBCON = 0x00044556;
120 #endif
121 rGPBUP = 0x000007FF;
122 rGPCCON = 0xAAAAAAAA;
123 rGPCUP = 0x0000FFFF;
124 rGPDCON = 0xAAAAAAAA;
125 rGPDUP = 0x0000FFFF;
126 rGPECON = 0xAAAAAAAA;
127 rGPEUP = 0x0000FFFF;
128 rGPFCON = 0x000055AA;
129 rGPFUP = 0x000000FF;
130 rGPGCON = 0xFF95FFBA;
131 rGPGUP = 0x0000FFFF;
132 rGPHCON = 0x002AFAAA;
133 rGPHUP = 0x000007FF;
134 #if 0/* snallie */
135 rEXTINT0=0x22222222;
136 rEXTINT1=0x22222222;
137 rEXTINT2=0x22222222;
138 #endif /* snallie */
/*
* 114~138 配置GPIO
*/
139
140 #if defined(CONFIG_SMDK2410) // snallie
141 /* arch number of SMDK2410-Board */
142 bd->bi_arch_number = 193;
143 #endif // snallie
144
145 #if defined(CONFIG_MINI2440) // snallie
146 /* arch number of MINI2440-Board */
147 bd->bi_arch_number = CONFIG_MACH_MINI2440; //782;
148 #endif // snallie
149 /* adress of boot parameters */
150 bd->bi_boot_params = 0x30000100;
/*
* 145~150 设置开发板的machine_ie,以及Kernel的启动参数的位置存放地址0x30000100
*/
151
152 #if defined(CONFIG_MINI2440) && defined(CONFIG_MINI2440_LED) /* snallie */
153 rGPBDAT = 0x00000180; /* led on , buzzer off( b0=0 ), snallie */
154 #endif /* snallie */
/*
* 152~154 设置开发板的led1，led2 为点亮状态，蜂鸣器关闭
*/
155 return 1;
156 }
157
158 int dram_init(bd_t *bd)
159 {
160 bd->bi_dram[0].start = PHYS_SDRAM_1;
161 bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
162 return PHYS_SDRAM_1_SIZE;
163 }
164
/////////////
修改common/armlinux.c 实现引导Linux Kernel，如下：
(引导kernel时应该个kernel送3个参数，放在r0,r1,r2寄存器中，r0=0,r1=machine_id,r2=parameter_addr)
1 /*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH
4 * Marius Groeger
5 *
6 * Copyright (C) 2001 Erik Mouw ([email protected])
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 */
23
24 #include "armboot.h"
25 #include "command.h"
26 #include "cmd_boot.h"
27 #include "image.h"
28 #include "malloc.h"
29 #include "zlib.h"
30
31 #include
32 #define tag_size(type) ((sizeof(struct tag_header) + sizeof(struct type)) >> 2)
33 #define tag_next(t) ((struct tag *)((u32 *)(t) + (t)->hdr.size))
34
35 static void setup_start_tag(bd_t *bd);
36 static void setup_memory_tags(bd_t *bd);
37 static void setup_commandline_tag(bd_t *bd, char *commandline);
38 #if 0
39 static void setup_ramdisk_tag(bd_t *bd);
40 #endif
41 static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end);
42 static void setup_end_tag(bd_t *bd);
43
44 extern image_header_t header; /* from cmd_bootm.c */
45
46 #undef DEBUG
47
48 static struct tag *params;
49
50 void boot_linux(cmd_tbl_t *cmdtp,
51 bd_t *bd, int flag,
52 int argc, char *argv[],
53 ulong addr,
54 ulong *len_ptr,
55 int verify)
56 {
57 ulong len = 0, checksum;
58 ulong initrd_start, initrd_end;
59 ulong data;
60 char *commandline = getenv(bd, "bootargs");
61 //void (*theKernel)(int zero, int arch); // snallie
62 void (*theKernel)(int zero, int arch, unsigned long param);
/*
* 62行重新声明Linux 的入口为一个函数的指针theKernel：启动kernel时要给其送3个参数：
* r0=0,r1=machine_id,r2=parameter_addr
*/
63 image_header_t *hdr = &header;
64 char *p_mach_id=NULL; // snallie
65 unsigned long mach_id=0; // snallie
/*
* 64~65行声明变量以存放machine_id
*/
66
67 /*
68 * Check if there is an initrd image
69 */
70 if (argc >= 3) {
71 addr = simple_strtoul(argv[2], NULL, 16);
72
73 printf ("## Loading Ramdisk Image at %08lx .../n", addr);
74
75 /* Copy header so we can blank CRC field for re-calculation */
76 memcpy (&header, (char *)addr, sizeof(image_header_t));
77
78 if (SWAP32(hdr->ih_magic) != IH_MAGIC) {
79 printf ("Bad Magic Number/n");
80 do_reset (cmdtp, bd, flag, argc, argv);
81 }
82
83 data = (ulong)&header;
84 len = sizeof(image_header_t);
85
86 checksum = SWAP32(hdr->ih_hcrc);
87 hdr->ih_hcrc = 0;
88
89 if (crc32 (0, (char *)data, len) != checksum) {
90 printf ("Bad Header Checksum/n");
91 do_reset (cmdtp, bd, flag, argc, argv);
92 }
93
94 print_image_hdr (hdr);
95
96 data = addr + sizeof(image_header_t);
97 len = SWAP32(hdr->ih_size);
98
99 if (verify) {
100 ulong csum = 0;
101
102 printf (" Verifying Checksum ... ");
103 csum = crc32 (0, (char *)data, len);
104 if (csum != SWAP32(hdr->ih_dcrc)) {
105 printf ("Bad Data CRC/n");
106 do_reset (cmdtp, bd, flag, argc, argv);
107 }
108 printf ("OK/n");
109 }
110
111 if ((hdr->ih_os != IH_OS_LINUX) ||
112 (hdr->ih_arch != IH_CPU_ARM) ||
113 (hdr->ih_type != IH_TYPE_RAMDISK) ) {
114 printf ("No Linux ARM Ramdisk Image/n");
115 do_reset (cmdtp, bd, flag, argc, argv);
116 }
117
118 /*
119 * Now check if we have a multifile image
120 */
121 } else if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1])) {
122 ulong tail = SWAP32(len_ptr[0]) % 4;
123 int i;
124
125 /* skip kernel length and terminator */
126 data = (ulong)(&len_ptr[2]);
127 /* skip any additional image length fields */
128 for (i=1; len_ptr[i]; ++i)
129 data += 4;
130 /* add kernel length, and align */
131 data += SWAP32(len_ptr[0]);
132 if (tail) {
133 data += 4 - tail;
134 }
135
136 len = SWAP32(len_ptr[1]);
137
138 } else {
139 /*
140 * no initrd image
141 */
142 data = 0;
143 }
144
145 #ifdef DEBUG
146 if (!data) {
147 printf ("No initrd/n");
148 }
149 #endif
150
151 if (data) {
152 initrd_start = data;
153 initrd_end = initrd_start + len;
154 printf (" Loading Ramdisk to %08lx, end %08lx ... ",
155 initrd_start, initrd_end);
156 memmove ((void *)initrd_start, (void *)data, len);
157 printf ("OK/n");
158 } else {
159 initrd_start = 0;
160 initrd_end = 0;
161 }
162
163 //theKernel = (void (*)(int, int))SWAP32(hdr->ih_ep); // snallie
164 theKernel = (void (*)(int, int, unsigned long))SWAP32(hdr->ih_ep);
/*
* 164行给 theKernel 赋值，以指向Linux kernel 的入口
*/
165
166 #ifdef DEBUG
167 printf ("## Transferring control to Linux (at address %08lx) .../n",
168 (ulong)theKernel);
169 #endif
170
171 setup_start_tag(bd);
172 setup_memory_tags(bd);
173 setup_commandline_tag(bd, commandline);
174 setup_initrd_tag(bd, initrd_start, initrd_end);
175 #if 0
176 setup_ramdisk_tag(bd);
177 #endif
178 setup_end_tag(bd);
179
180 /* we assume that the kernel is in place */
181 printf("/nStarting kernel .../n/n");
182
183 cleanup_before_linux(bd);
184
185 //theKernel(0, bd->bi_arch_number); // snallie
186 if((p_mach_id=getenv(bd,"mach_id"))!=NULL) {
187 mach_id=simple_strtoul(p_mach_id,NULL,10);
188 theKernel(0, mach_id ,bd->bi_boot_params); // snallie
/*
* 186行 读取环境变量 mach_id，若该环境变量存在，则将该值取出，传递给theKernel以启动Linux Kernel
*/
189 }
190 else{
191 theKernel(0, bd->bi_arch_number,bd->bi_boot_params); // snallie
/*
* 191行 若该环境变量不存在，则将 board_info中存放的bi_arch_number作为machine_id，传递给theKernel以启动Linux Kernel
*/
192 }
193 }
194
195
196 static void setup_start_tag(bd_t *bd)
197 {
198 params = (struct tag *)bd->bi_boot_params;
199
200 params->hdr.tag = ATAG_CORE;
201 params->hdr.size = tag_size(tag_core);
202
203 params->u.core.flags = 0;
204 params->u.core.pagesize = 0;
205 params->u.core.rootdev = 0;
206
207 params = tag_next(params);
208 }
209
210
211 static void setup_memory_tags(bd_t *bd)
212 {
213 int i;
214
215 for(i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
216 params->hdr.tag = ATAG_MEM;
217 params->hdr.size = tag_size(tag_mem32);
218
219 params->u.mem.start = bd->bi_dram[i].start;
220 params->u.mem.size = bd->bi_dram[i].size;
221
222 params = tag_next(params);
223 }
224 }
225
226
227 static void setup_commandline_tag(bd_t *bd, char *commandline)
228 {
229 char *p;
230
231 /* eat leading white space */
232 for(p = commandline; *p == ' '; p++)
233 ;
234
235 /* skip non-existent command lines so the kernel will still
236 * use its default command line.
237 */
238 if(*p == '/0')
239 return;
240
241 params->hdr.tag = ATAG_CMDLINE;
242 params->hdr.size = (sizeof(struct tag_header) + strlen(p) + 1 + 4) >> 2;
243
244 strcpy(params->u.cmdline.cmdline, p);
245
246 params = tag_next(params);
247 }
248
249
250 static void setup_initrd_tag(bd_t *bd, ulong initrd_start, ulong initrd_end)
251 {
252 /* an ATAG_INITRD node tells the kernel where the compressed
253 * ramdisk can be found. ATAG_RDIMG is a better name, actually.
254 */
255 params->hdr.tag = ATAG_INITRD;
256 params->hdr.size = tag_size(tag_initrd);
257
258 params->u.initrd.start = initrd_start;
259 params->u.initrd.size = initrd_end - initrd_start;
260
261 params = tag_next(params);
262 }
263
264
265 #if 0
266 static void setup_ramdisk_tag(bd_t *bd)
267 {
268 /* an ATAG_RAMDISK node tells the kernel how large the
269 * decompressed ramdisk will become.
270 */
271 params->hdr.tag = ATAG_RAMDISK;
272 params->hdr.size = tag_size(tag_ramdisk);
273
274 params->u.ramdisk.start = 0;
275 //params->u.ramdisk.size = RAMDISK_SIZE;
276 params->u.ramdisk.flags = 1; /* automatically load ramdisk */
277
278 params = tag_next(params);
279 }
280 #endif
281
282 static void setup_end_tag(bd_t *bd)
283 {
284 params->hdr.tag = ATAG_NONE;
285 params->hdr.size = 0;
286 }
/////////
修改common/cmd_nvedit.c ，加入环境变量mach_id,如下：
1 /*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, [email protected].
4 *
5 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH
6 * Andreas Heppel
7
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27 /*
28 * Support for persistent environment data
29 */
30
31 #include "armboot.h"
32 #include "command.h"
33 #include "malloc.h"
34 #include "cmd_nvedit.h"
35
36 #if (CONFIG_COMMANDS & CFG_CMD_NET)
37 #include "net.h"
38 #endif
39
40 /*
41 * Table with supported baudrates (defined in config_xyz.h)
42 */
43 static const unsigned long baudrate_table[] = CFG_BAUDRATE_TABLE;
44 #define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0]))
45
46 /*
47 * Default settings to be used when no valid environment is found
48 */
49 #define XMK_STR(x) #x
50 #define MK_STR(x) XMK_STR(x)
51
52 uchar default_environment[] = {
53 #ifdef CONFIG_BOOTARGS
54 "bootargs=" CONFIG_BOOTARGS "/0"
55 #endif
56 #ifdef CONFIG_BOOTCOMMAND
57 "bootcmd=" CONFIG_BOOTCOMMAND "/0"
58 #endif
59 #ifdef CONFIG_RAMBOOTCOMMAND
60 "ramboot=" CONFIG_RAMBOOTCOMMAND "/0"
61 #endif
62 #ifdef CONFIG_NFSBOOTCOMMAND
63 "nfsboot=" CONFIG_NFSBOOTCOMMAND "/0"
64 #endif
65 #if defined(CONFIG_BOOTDELAY) && (CONFIG_BOOTDELAY >= 0)
66 "bootdelay=" MK_STR(CONFIG_BOOTDELAY) "/0"
67 #endif
68 #if defined(CONFIG_BAUDRATE) && (CONFIG_BAUDRATE >= 0)
69 "baudrate=" MK_STR(CONFIG_BAUDRATE) "/0"
70 #endif
71 #ifdef CONFIG_LOADS_ECHO
72 "loads_echo=" MK_STR(CONFIG_LOADS_ECHO) "/0"
73 #endif
74 #ifdef CONFIG_ETHADDR
75 "ethaddr=" MK_STR(CONFIG_ETHADDR) "/0"
76 #endif
77 #ifdef CONFIG_ETH2ADDR
78 "eth2addr=" MK_STR(CONFIG_ETH2ADDR) "/0"
79 #endif
80 #ifdef CONFIG_ETH3ADDR
81 "eth3addr=" MK_STR(CONFIG_ETH3ADDR) "/0"
82 #endif
83 #ifdef CONFIG_IPADDR
84 "ipaddr=" MK_STR(CONFIG_IPADDR) "/0"
85 #endif
86 #ifdef CONFIG_SERVERIP
87 "serverip=" MK_STR(CONFIG_SERVERIP) "/0"
88 #endif
89 #ifdef CFG_AUTOLOAD
90 "autoload=" CFG_AUTOLOAD "/0"
91 #endif
92 #ifdef CONFIG_PREBOOT
93 "preboot=" CONFIG_PREBOOT "/0"
94 #endif
95 #ifdef CONFIG_ROOTPATH
96 "rootpath=" MK_STR(CONFIG_ROOTPATH) "/0"
97 #endif
98 #ifdef CONFIG_GATEWAYIP
99 "gatewayip=" MK_STR(CONFIG_GATEWAYIP) "/0"
100 #endif
101 #ifdef CONFIG_NETMASK
102 "netmask=" MK_STR(CONFIG_NETMASK) "/0"
103 #endif
104 #ifdef CONFIG_HOSTNAME
105 "hostname=" MK_STR(CONFIG_HOSTNAME) "/0"
106 #endif
107 #ifdef CONFIG_BOOTFILE
108 "bootfile=" MK_STR(CONFIG_BOOTFILE) "/0"
109 #endif
110 #ifdef CONFIG_LOADADDR
111 "loadaddr=" MK_STR(CONFIG_LOADADDR) "/0"
112 #endif
113 #ifdef CONFIG_CLOCKS_IN_MHZ
114 "clocks_in_mhz=1/0"
115 #endif
116 #ifdef CONFIG_MACH_MINI2440
117 "mach_id=" MK_STR(CONFIG_MACH_MINI2440) "/0" /* snallie */
118 #endif
/*
* 116~118定义了一个环境变量mach_id,其默认取值为include/configs/config_mini2440.h中定义的CONFIG_MACH_MINI2440，本文件只有此处改动
*/
119 "/0"
120 };
121
122 static int envmatch (bd_t *, uchar *, int);
123
124 /*
125 * return one character from env
126 */
127 static uchar get_env_char(bd_t *bd, int index)
128 {
129 uchar c;
130
131 /* use RAM copy, if possible */
132 if (bd->bi_env)
133 {
134 if (index < sizeof(bd->bi_env_data))
135 c = bd->bi_env_data[index];
136 else
137 panic("bad size for get_env_char!/n");
138 }
139 else
140 {
141 /* try a board specific lookup */
142 if (board_env_getchar(bd, index, &c) < 0)
143 {
144 if (index < sizeof(default_environment))
145 c = default_environment[index];
146 else
147 panic("bad size for get_env_char!/n");
148 }
149 }
150 return c;
151 }
152
153 /*
154 * return address into environment
155 */
156 static uchar *get_env_addr(bd_t *bd, int index)
157 {
158 uchar *p = 0;
159
160 /* use RAM copy, if possible */
161 if (bd->bi_env)
162 {
163 if (index < sizeof(bd->bi_env_data))
164 p = &bd->bi_env_data[index];
165 else
166 panic("bad size for get_env_char!/n");
167 }
168 else
169 {
170 /* try a board specific lookup */
171 if ((p = board_env_getaddr(bd, index)) == 0)
172 {
173 if (index < sizeof(default_environment))
174 p = &default_environment[index];
175 else
176 panic("bad size for get_env_char!/n");
177 }
178 }
179 return p;
180 }
181
182 /************************************************************************
183 * Command interface: print one or all environment variables
184 */
185
186 int do_printenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
187 {
188 int i, j, k, nxt;
189
190 if (argc == 1) { /* Print all env variables */
191 for (i=0; get_env_char(bd, i) != '/0'; i=nxt+1) {
192 for (nxt=i; get_env_char(bd, nxt) != '/0'; ++nxt)
193 ;
194 for (k=i; k
196 putc ('/n');
197
198 if (ctrlc()) {
199 printf ("/n ** Abort/n");
200 return 1;
201 }
202 }
203
204 printf("/nEnvironment size: %d/%d bytes/n", i, sizeof(bd->bi_env_data));
205
206 return 0;
207 }
208
209 for (i=1; i
211
212 k = -1;
213
214 for (j=0; get_env_char(bd, j) != '/0'; j=nxt+1) {
215
216 for (nxt=j; get_env_char(bd, nxt) != '/0'; ++nxt)
217 ;
218 k = envmatch(bd, name, j);
219 if (k < 0) {
220 continue;
221 }
222 puts (name);
223 putc ('=');
224 while (k < nxt)
225 putc(get_env_char(bd, k++));
226 putc ('/n');
227 break;
228 }
229 if (k < 0)
230 {
231 printf ("## Error: /"%s/" not defined/n", name);
232 return 1;
233 }
234 }
235 return 0;
236 }
237
238 /************************************************************************
239 * Set a new environment variable,
240 * or replace or delete an existing one.
241 *
242 * This function will ONLY work with a in-RAM copy of the environment
243 */
244
245 int _do_setenv (bd_t *bd, int flag, int argc, char *argv[])
246 {
247 int i, len, oldval;
248 uchar *env, *nxt = 0;
249 uchar *name;
250
251 /* need writable copy in RAM */
252 if (!bd->bi_env_data)
253 return 1;
254
255 name = argv[1];
256
257 /*
258 * search if variable with this name already exists
259 */
260 oldval = -1;
261 for (env = bd->bi_env_data; *env; env = nxt+1) {
262 for (nxt = env; *nxt; ++nxt)
263 ;
264 if ((oldval = envmatch(bd, name, (ulong)env - (ulong)bd->bi_env_data)) >= 0)
265 break;
266 }
267
268 /*
269 * Delete any existing definition
270 */
271 if (oldval >= 0) {
272 #ifndef CONFIG_ENV_OVERWRITE
273
274 /*
275 * Ethernet Address and serial# can be set only once
276 */
277 if ( (strcmp (name, "serial#") == 0) ||
278 ((strcmp (name, "ethaddr") == 0)
279 # if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR)
280 && (strcmp (get_env_addr(bd, oldval),MK_STR(CONFIG_ETHADDR)) != 0)
281 # endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */
282 ) ) {
283 printf ("Can't overwrite /"%s/"/n", name);
284 return 1;
285 }
286 #endif
287
288 /*
289 * Switch to new baudrate if new baudrate is supported
290 */
291 if (strcmp(argv[1],"baudrate") == 0) {
292 int baudrate = simple_strtoul(argv[2], NULL, 10);
293 int i;
294 for (i=0; i
296 break;
297 }
298 if (i == N_BAUDRATES) {
299 printf ("## Baudrate %d bps not supported/n",
300 baudrate);
301 return 1;
302 }
303 printf ("## Switch baudrate to %d bps and press ENTER .../n",
304 baudrate);
305 udelay(50000);
306 serial_setbrg (bd, baudrate);
307 udelay(50000);
308 for (;;) {
309 if (getc() == '/r')
310 break;
311 }
312 bd->bi_baudrate = baudrate;
313 }
314
315 if (*++nxt == '/0') {
316 if ((ulong)env > (ulong)bd->bi_env_data) {
317 env--;
318 } else {
319 *env = '/0';
320 }
321 } else {
322 for (;;) {
323 *env = *nxt++;
324 if ((*env == '/0') && (*nxt == '/0'))
325 break;
326 ++env;
327 }
328 }
329 *++env = '/0';
330 }
331 /* Delete only ? */
332 if ((argc < 3) || argv[2] == NULL) {
333 /* Update CRC */
334 bd->bi_env_crc = crc32(0, bd->bi_env_data, sizeof(bd->bi_env_data));
335 return 0;
336 }
337
338 /*
339 * Append new definition at the end
340 */
341 for (env = bd->bi_env_data; *env || *(env+1); ++env)
342 ;
343 if ((ulong)env > (ulong)bd->bi_env_data)
344 ++env;
345 /*
346 * Overflow when:
347 * "name" + "=" + "val" +"/0/0" >
348 * sizeof(bd->bi_env_data) - (env-bd->bi_env_data)
349 */
350 len = strlen(name) + 2;
351 /* add '=' for first arg, ' ' for all others */
352 for (i=2; i
354 }
355 if (len > sizeof(bd->bi_env_data)) {
356 printf ("## Error: environment overflow, /"%s/" deleted/n", name);
357 return 1;
358 }
359 while ((*env = *name++) != '/0')
360 env++;
361 for (i=2; i
363
364 *env = (i==2) ? '=' : ' ';
365 while ((*++env = *val++) != '/0')
366 ;
367 }
368
369 /* end is marked with double '/0' */
370 *++env = '/0';
371
372 /* Update CRC */
373 bd->bi_env_crc = crc32(0, bd->bi_env_data, sizeof(bd->bi_env_data));
374
375 /*
376 * Some variables should be updated when the corresponding
377 * entry in the enviornment is changed
378 */
379
380 if (strcmp(argv[1],"ethaddr") == 0) {
381 char *s = argv[2]; /* always use only one arg */
382 char *e;
383 for (i=0; i<6; ++i) {
384 bd->bi_enetaddr[i] = s ? simple_strtoul(s, &e, 16) : 0;
385 if (s) s = (*e) ? e+1 : e;
386 }
387 return 0;
388 }
389
390 if (strcmp(argv[1],"ipaddr") == 0) {
391 char *s = argv[2]; /* always use only one arg */
392 char *e;
393 bd->bi_ip_addr = 0;
394 for (i=0; i<4; ++i) {
395 ulong val = s ? simple_strtoul(s, &e, 10) : 0;
396 bd->bi_ip_addr <<= 8;
397 bd->bi_ip_addr |= (val & 0xFF);
398 if (s) s = (*e) ? e+1 : e;
399 }
400 return 0;
401 }
402
403 if (strcmp(argv[1],"loadaddr") == 0) {
404 load_addr = simple_strtoul(argv[2], NULL, 16);
405 return 0;
406 }
407
408 #if (CONFIG_COMMANDS & CFG_CMD_NET)
409 if (strcmp(argv[1],"bootfile") == 0) {
410 copy_filename (BootFile, argv[2], sizeof(BootFile));
411 return 0;
412 }
413 #endif /* CFG_CMD_NET */
414
415 return 0;
416 }
417
418 void setenv (bd_t * bd, char *varname, char *varvalue)
419 {
420 char *argv[4] = { "setenv", varname, varvalue, NULL };
421 _do_setenv (bd, 0, 3, argv);
422 }
423
424 int do_setenv (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc,
425 char *argv[])
426 {
427 if (argc < 2) {
428 printf ("Usage:/n%s/n", cmdtp->usage);
429 return 1;
430 }
431
432 return _do_setenv (bd, flag, argc, argv);
433 }
434
435 /************************************************************************
436 * Prompt for environment variable
437 */
438
439 #if (CONFIG_COMMANDS & CFG_CMD_ASKENV)
440 int do_askenv (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc,
441 char *argv[])
442 {
443 extern char console_buffer[CFG_CBSIZE];
444 char message[CFG_CBSIZE];
445 int size = CFG_CBSIZE - 1;
446 int len;
447 char *local_args[4];
448
449 local_args[0] = argv[0];
450 local_args[1] = argv[1];
451 local_args[2] = NULL;
452 local_args[3] = NULL;
453
454 if (argc < 2) {
455 printf ("Usage:/n%s/n", cmdtp->usage);
456 return 1;
457 }
458 /* Check the syntax */
459 switch (argc) {
460 case 1:
461 printf ("Usage:/n%s/n", cmdtp->usage);
462 return 1;
463
464 case 2: /* askenv envname */
465 sprintf (message, "Please enter '%s':", argv[1]);
466 break;
467
468 case 3: /* askenv envname size */
469 sprintf (message, "Please enter '%s':", argv[1]);
470 size = simple_strtoul (argv[2], NULL, 10);
471 break;
472
473 default: /* askenv envname message1 ... messagen size */
474 {
475 int i;
476 int pos = 0;
477
478 for (i = 2; i < argc - 1; i++) {
479 if (pos) {
480 message[pos++] = ' ';
481 }
482 strcpy (message+pos, argv[i]);
483 pos += strlen(argv[i]);
484 }
485 message[pos] = '/0';
486 size = simple_strtoul (argv[argc - 1], NULL, 10);
487 }
488 }
489
490 if (size >= CFG_CBSIZE)
491 size = CFG_CBSIZE - 1;
492
493 if (size <= 0)
494 return 1;
495
496 /* prompt for input */
497 len = readline (message);
498
499 if (size < len)
500 console_buffer[size] = '/0';
501
502 len = 2;
503 if (console_buffer[0] != '/0') {
504 local_args[2] = console_buffer;
505 len = 3;
506 }
507
508 // Continue calling setenv code
509 return _do_setenv (bd, flag, len, local_args);
510 }
511 #endif /* CFG_CMD_ASKENV */
512
513 /************************************************************************
514 * Look up variable from environment,
515 * return address of storage for that variable,
516 * or NULL if not found
517 */
518
519 char *getenv (bd_t * bd, uchar *name)
520 {
521 int i, nxt;
522
523 for (i=0; get_env_char(bd, i) != '/0'; i=nxt+1) {
524 int val;
525
526 for (nxt=i; get_env_char(bd, nxt) != '/0'; ++nxt) {
527 if (nxt >= sizeof(bd->bi_env_data)) {
528 return (NULL);
529 }
530 }
531 if ((val=envmatch(bd, name, i)) < 0)
532 continue;
533 return (get_env_addr(bd, val));
534 }
535
536 return (NULL);
537 }
538
539
540 /************************************************************************
541 * Match a name / name=value pair
542 *
543 * s1 is either a simple 'name', or a 'name=value' pair.
544 * i2 is the environment index for a 'name2=value2' pair.
545 * If the names match, return the index for the value2, else NULL.
546 */
547
548 static int envmatch (bd_t *bd, uchar *s1, int i2)
549 {
550
551 while (*s1 == get_env_char(bd, i2++))
552 if (*s1++ == '=')
553 return(i2);
554 if (*s1 == '/0' && get_env_char(bd, i2-1) == '=')
555 return(i2);
556 return(-1);
557 }
558
559
560 #if (CONFIG_COMMANDS & CFG_CMD_ENV)
561
562 int do_saveenv (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
563 {
564 return (board_env_save(bd, bd->bi_env, sizeof(env_t))) ? 1 : 0;
565 }
566
567 #endif /* CFG_CMD_ENV */
568
569
570 void env_init(bd_t *bd)
571 {
572 bd->bi_env = 0;
573 }
574
575 void env_relocate(bd_t *bd)
576 {
577 char *s, *e;
578 int reg;
579
580 bd->bi_env = malloc(sizeof(env_t));
581
582 if (board_env_copy(bd, bd->bi_env, sizeof(env_t)) < 0)
583 {
584 printf("*** Using default environment/n");
585 memcpy(bd->bi_env_data, default_environment,
586 sizeof(default_environment));
587 bd->bi_env_crc = crc32(0, bd->bi_env_data, sizeof(bd->bi_env_data));
588 }
589
590 /* now initialise some variables */
591
592 /* MAC address */
593 s = getenv(bd, "ethaddr");
594 for (reg=0; reg<6; reg++)
595 {
596 bd->bi_enetaddr[reg] = s ? simple_strtoul(s, &e, 16) : 0;
597 if (s)
598 s = (*e) ? e+1 : e;
599 }
600
601 /* IP address */
602 bd->bi_ip_addr = 0;
603 s = getenv(bd, "ipaddr");
604 for (reg=0; reg<4; ++reg) {
605 ulong val = s ? simple_strtoul(s, &e, 10) : 0;
606 bd->bi_ip_addr <<= 8;
607 bd->bi_ip_addr |= (val & 0xFF);
608 if (s)
609 s = (*e) ? e+1 : e;
610 }
611
612 if ((s = getenv(bd, "loadaddr")) != NULL) {
613 load_addr = simple_strtoul(s, NULL, 16);
614 }
615
616 #if (CONFIG_COMMANDS & CFG_CMD_NET)
617 if ((s = getenv(bd, "bootfile")) != NULL) {
618 copy_filename (BootFile, s, sizeof(BootFile));
619 }
620 #endif /* CFG_CMD_NET */
621 }
/////////////
修改 common/command.c ，加入nboot命令 以启动 zImage 形式的Linux内核，如下：
1 /*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, [email protected].
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 /*
25 * Command Processor Table
26 */
27
28 #include
29 #include
30 #include
31 #include
32 #include
33 #include
34 #include
35 #include
36 #include
37 #include
38 #include
39 #include
40 #include
41 #include
42
43 #include
44 #include
45
46 #include
47 #include "asm/setup.h" // snallie
/* 47行包含头文件asm/setup.h, 用到其中的Linux Kernel参数结构体的定义 struct param_struct */
48
49 /*
50 * HELP command
51 */
52 #define CMD_TBL_HELP MK_CMD_TBL_ENTRY( /
53 "help", 1, CFG_MAXARGS, 1, do_help, /
54 "help - print online help/n", /
55 "[command ...]/n" /
56 " - show help information (for 'command')/n" /
57 "'help' prints online help for the monitor commands./n/n" /
58 "Without arguments, it prints a short usage message for all commands./n/n" /
59 "To get detailed help information for specific commands you can type/n" /
60 "'help' with one or more command names as arguments./n" /
61 ),
62
63 #define CMD_TBL_QUES MK_CMD_TBL_ENTRY( /
64 "?", 1, CFG_MAXARGS, 1, do_help, /
65 "? - alias for 'help'/n", /
66 NULL /
67 ),
68
69 #define CMD_TBL_VERS MK_CMD_TBL_ENTRY( /
70 "version", 4, 1, 1, do_version, /
71 "version - print monitor version/n", /
72 NULL /
73 ),
74
75 #define CMD_TBL_ECHO MK_CMD_TBL_ENTRY( /
76 "echo", 4, CFG_MAXARGS, 1, do_echo, /
77 "echo - echo args to console/n", /
78 "[args..]/n" /
79 " - echo args to console; //c suppresses newline/n" /
80 ),
81
82 // snallie
83 #define CMD_TBL_NBOOT MK_CMD_TBL_ENTRY( /
84 "nboot", 3, CFG_MAXARGS, 1, do_nboot, /
85 "nboot - boot Linux kernel from nand/n", /
86 "[loadaddr kernel_offset_on_NAND kernel_size]/n" /
87 ),
/* 83~87行的宏定义CMD_TBL_NBOOT可以产生nboot命令的结构体表项 */
88
89 int do_nboot (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[]) /* boot zImage */
90 {
91 extern int CopyCode2Ram( unsigned long start_addr, unsigned char *buf, int size);
/* 91行声明CopyCode2Ram函数的原型，该函数位于 board/mini2440/boot_init.c 中 */
92 struct param_struct *p = (struct param_struct *)0x30000100;
/* 92行定义了Linux参数的结构体的指针，并赋值为0x30000100，接传递个内核的参数放到0x30000100其实处的内存中 */
93 void (*theKernel)(int zero, int arch, unsigned long params);
/* 92行定义了Linux kernel的入口指针 */
94 char *p_args;
95 char *p_mach_id=NULL; // snallie
96 unsigned long mach_id=0; // snallie
/*
* 95~96 用mach_id存放machine_id,以供启动内核之用
*/
97
98 if( argc!=1 && argc!=4 )
99 {
100 printf ( "Usage:/n%s %s/n",cmdtp->name ,cmdtp->usage);
101 return 1;
102 }
/*
* 98~102 判断 nboot 的命令格式是否正确，nboot的正确格式为两种：
* 1) 只有命令名的默认格式,没有任何参数：nboot
* 2）有三个必选参数，形式为：nboot loadaddr kernel_offset_on_NAND kernel_size
* 如： nboot 0x30008000 0x50000 0x200000
* 表示将为与Flash上的偏移为0x50000地址处的0x200000字节的kernel读到0x30008000地址处
* 如果命令的格式不正确，则显示提示信息，而后返回。
*/
103
104 printf ("/nReading kernel.../n");
105 switch( argc )
106 {
107 case 1: /* load default */
108 CopyCode2Ram(CONFIG_KERNEL_OFFSET_ON_NAND ,(unsigned char *)CONFIG_LOADADDR, CONFIG_KERNEL_SIZE );
109 break;
/*
* 107~109行，若nboot为默认格式，则取配置文件的参数，CONFIG_KERNEL_OFFSET_ON_NAND，CONFIG_LOADADDR， CONFIG_KERNEL_SIZE，来调用CopyCode2Ram
* CopyCode2Ram的功能为将Linux kernel 从Flash上读到RAM中
*/
110
111 case 4: /* load customized */
112 CopyCode2Ram(simple_strtoul(argv[1], NULL, 16 ),(unsigned char *)simple_strtoul(argv[2], NULL, 16 ),simple_strtoul(argv[3], NULL, 16 ) );
113 break;
/*
* 111~113行，若nboot三个必选参数齐全，则用这些命令行上提供的参数其调用CopyCode2Ram
*/
114
115 default:
116 return 1;
117 }
118
119 #define LINUX_CMD_LINE CONFIG_BOOTARGS
120 #define g_linux_cmd_line LINUX_CMD_LINE
121
122 memset(p, 0, sizeof(*p));
123 if ((p_args = getenv (bd,"bootargs")) != NULL) {
124 memcpy(p->commandline, p_args, strlen(p_args));
125 }
/*
* 123~125行， 判断环境变量bootargs存在否，若存在，则将其读到参数结构体中的commandline部分
*/
126 else{
127 memcpy(p->commandline, g_linux_cmd_line, sizeof(g_linux_cmd_line));
128 }
/*
* 126~128行， 环境变量bootargs不存在，则取 include/configs/config_mini2440.h中的配置，将其读到参数结构体中的commandline部分
*/
129
130 p->u1.s.page_size = 4 * 1024;
131 p->u1.s.nr_pages = 64 * 1024 * 1024 / (4 * 1024);
/*
* 130~131行，传递给Linux Kernel 的参数结构体中设定RAM的页面单位大小，以及页的个数，MINI2440有64MB RAM
*/
132 {
133 #ifdef CONFIG_LOADADDR
134 unsigned int *pp = (unsigned int *)( CONFIG_LOADADDR+0x24);
135 #else
136 unsigned int *pp = (unsigned int *)(simple_strtoul(argv[2], NULL, 16 )+0x24);
137 #endif
138
139 if (pp[0] == 0x016f2818) { // Magic number of zImage
140 printf("/n/rOk/n/r");
141 } else {
142 printf("/n/rWrong Linux Kernel/n/r");
143 for (;;) ;
144 }
145 }
/*
* 判断Linux Kernel的魔数是否正确，魔数在Linux kernel映像头部的偏移0x24处
*/
146
147 printf( "Starting Linux kernel.../n");
148
149 #ifdef CONFIG_LOADADDR
150 theKernel = (void (*)(int, int, unsigned long))( CONFIG_LOADADDR);
151 #else
152 theKernel = (void (*)(int, int, unsigned long))(simple_strtoul(argv[2], NULL, 16 ));
153 #endif
/*
* 149~153给Linux Kernel的入口指针theKernel 赋以值正确的值，默认zImage的入口地址在0x30008000处。
*/
154 //theKernel(0, bd->bi_arch_number, bd->bi_boot_params); // snallie
155 if((p_mach_id=getenv(bd,"mach_id"))!=NULL) {
156 mach_id=simple_strtoul(p_mach_id,NULL,10);
157 theKernel(0, mach_id ,bd->bi_boot_params); // snallie
/*
* 155~157 判断环境变量mach_id是否存在，若存在则将其取出，传递给Linux Kernel，157行跳转到Kernel入口 ，
* zImage的入口地址在0x30008000处，启动kernel ,若正确的话，将看到
* Uncompressing Linux.................................................................................... done, booting the kernel.
* Linux version 2.6.29.4 ...
* ....
* 的输出信息，证明Kernel 已经正确引导启动。
* 若启动时停在 done, booting the kernel.，有可能为传递给Kernel的Machine_id 不对，可以重设环境变量mach_id：方法为在armboot的命令提示符下输入命令：
* ARMboot@MINI2440 # setenv mach_id 1999
* 就将环境变量mach_id设为1999
*/
158 }
159 else{
160 theKernel(0, bd->bi_arch_number,bd->bi_boot_params); // snallie
161 }
/*
* 159~161 若环境变量mach_id不存在，则将bd_info结构体存放的默认参数传递 给Linux Kernel，160行跳转到Kernel入口启动kernel，启动信息和上面155~157的注释相同。
* 到此，则ARMboot的历史使命就结束了，Linux Kernel接管了机器的总体控制。底下的162~180的代码也不会执行到了。
*/
162
163 #if 0
164 asm volatile (
165 "mov r5, %3/n"
166 "mov r0, #0/n"
167 "mov r1, %1/n"
168 "mov r2, %2/n"
169 "mov pc, r5/n"
170 "nop/n" "nop/n": /* no outpus */
171 :"r"(0), "r"(bd->bi_arch_number), "r"(bd->bi_boot_params),
172 #ifdef CONFIG_LOADADDR
173 "r"(CONFIG_LOADADDR)
174 #else
175 "r"(simple_strtoul(argv[2], NULL, 16 ))
176 #endif
177 );
178 #endif
179
180 return 0;
181 }
182 // snallie
/* 89~181行为nboot命令的的具体动作的内容 */
183
184 int do_version (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
185 {
186 extern char version_string[];
187 printf ("/n%s/n", version_string);
188 return 0;
189 }
190
191 int do_echo (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
192 {
193 int i, putnl = 1;
194
195 for (i = 1; i < argc; i++) {
196 char *p = argv[i], c;
197
198 if (i > 1)
199 putc(' ');
200 while ((c = *p++) != '/0')
201 if (c == '//' && *p == 'c') {
202 putnl = 0;
203 p++;
204 }
205 else
206 putc(c);
207 }
208
209 if (putnl)
210 putc('/n');
211
212 return 0;
213 }
214
215 /*
216 * Use puts() instead of printf() to avoid printf buffer overflow
217 * for long help messages
218 */
219 int do_help (cmd_tbl_t *cmdtp, bd_t *bd, int flag, int argc, char *argv[])
220 {
221 int i;
222
223 if (argc == 1) { /* print short help (usage) */
224
225 for (cmdtp=&cmd_tbl[0]; cmdtp->name; cmdtp++) {
226 /* allow user abort */
227 if (ctrlc())
228 return 1;
229
230 if (cmdtp->usage == NULL)
231 continue;
232 puts (cmdtp->usage);
233 }
234
235 return 0;
236 }
237
238 /*
239 * command help (long version)
240 */
241 for (i=1; i
243 #ifdef CFG_LONGHELP
244 /* found - print (long) help info */
245 puts (cmdtp->name);
246 putc (' ');
247 if (cmdtp->help) {
248 puts (cmdtp->help);
249 } else {
250 puts ("- No help available./n");
251 }
252 putc ('/n');
253 #else /* no long help available */
254 if (cmdtp->usage)
255 puts (cmdtp->usage);
256 #endif /* CFG_LONGHELP */
257 }
258 else {
259 printf ("Unknown command '%s' - try 'help'"
260 " without arguments for list of all"
261 " known commands/n/n",
262 argv[i]
263 );
264 }
265 }
266 return 0;
267 }
268
269 /***************************************************************************
270 * find command table entry for a command
271 */
272 cmd_tbl_t *find_cmd(const char *cmd)
273 {
274 cmd_tbl_t *cmdtp;
275
276 /* Search command table - Use linear search - it's a small table */
277 for (cmdtp = &cmd_tbl[0]; cmdtp->name; cmdtp++) {
278 if (strncmp (cmd, cmdtp->name, cmdtp->lmin) == 0)
279 return cmdtp;
280 }
281 return NULL; /* not found */
282 }
283
284 cmd_tbl_t cmd_tbl[] = {
285 CMD_TBL_GO
286 CMD_TBL_RUN
287
288 CMD_TBL_BOOTM
289 CMD_TBL_BOOTP
290 CMD_TBL_TFTPB
291 CMD_TBL_RARPB
292 CMD_TBL_DHCP
293 CMD_TBL_BOOTD
294 CMD_TBL_LOADS
295 CMD_TBL_LOADB
296 CMD_TBL_AUTOSCRIPT
297 CMD_TBL_MD
298 CMD_TBL_MM
299 CMD_TBL_NM
300 CMD_TBL_MW
301 CMD_TBL_CP
302 CMD_TBL_CMP
303 CMD_TBL_CRC
304 CMD_TBL_BASE
305 CMD_TBL_PRINTENV
306 CMD_TBL_SETENV
307 CMD_TBL_ASKENV
308 CMD_TBL_SAVEENV
309 CMD_TBL_PROTECT
310 CMD_TBL_FLERASE
311 CMD_TBL_FLINFO
312 CMD_TBL_BDINFO
313 CMD_TBL_IMINFO
314 CMD_TBL_EEPROM
315 CMD_TBL_LOOP
316 CMD_TBL_MTEST
317 CMD_TBL_ICACHE
318 CMD_TBL_DCACHE
319 CMD_TBL_RESET
320 CMD_TBL_ECHO
321 CMD_TBL_IDE
322 CMD_TBL_DISK
323 CMD_TBL_PINIT
324 CMD_TBL_JFFS2
325 CMD_TBL_MISC
326 #ifdef CMD_TBL_BSP /* Board Specific extensions ? */
327 CMD_TBL_BSP
328 #endif
329 CMD_TBL_VERS
330 CMD_TBL_HELP
331 CMD_TBL_QUES
332 CMD_TBL_NBOOT /* snallie */
/*
* 332行的 CMD_TBL_NBOOT 将导致在命令的结构体数组中加入一个新的表项，把nboot命令的相关信息导入，否则nboot命令是找不到的，也不可能执行。
*/
333 /* the following entry terminates this table */
334 MK_CMD_TBL_ENTRY( NULL, 0, 0, 0, NULL, NULL, NULL )
335 };
//////////////
修改common/display_options.c ,加入个性化的启动信息，如下：
1 /*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, [email protected].
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #include "version.h"
25 #include "armboot.h"
26
27 const char version_string[] =
28 ARMBOOT_VERSION " (" __DATE__ " - " __TIME__ ")";
29
30 void display_banner(bd_t *bd)
31 {
32 printf ("/n/n%s/n/n", version_string);
33 printf("You know that ARMboot is the ancestor of U-boot project./n"); // snallie
34 printf("Rebuilt to accommodate the MINI2440 board, by [email protected]/nFeb 11 2011 ~ %s/n", __DATE__); //snallie
35 printf("gcc version: %s/n/n",__VERSION__); // snallie
/*
* 33~35行显示个性化的启动信息，并显示所用的交叉编译器的版本信息. 本文件只修改该处
*/
36
37 printf("ARMboot code: %08lx -> %08lx/n", _armboot_start, _armboot_end);
38 #ifdef CONFIG_USE_IRQ
39 printf("IRQ Stack: %08lx/n", IRQ_STACK_START);
40 printf("FIQ Stack: %08lx/n", FIQ_STACK_START);
41 #endif
42 }
43
44 static void pretty_print_size(ulong size)
45 {
46 if (size > 0x100000)
47 printf("%ld MB", size / 0x100000);
48 else
49 printf("%ld KB", size / 0x400);
50 }
51
52 void display_dram_config(bd_t *bd)
53 {
54 int i;
55
56 printf("DRAM Configuration:/n");
57
58 for(i=0; i
60 printf("Bank #%d: %08lx ", i, bd->bi_dram[i].start);
61 pretty_print_size(bd->bi_dram[i].size);
62 printf("/n");
63 }
64 }
65
66 void display_flash_config(bd_t *bd, ulong size)
67 {
68 printf("Flash: ");
69 pretty_print_size(size);
70 printf("/n");
71 }
//////////
全部的修改完毕，编译测试：
[root@arm armboot-1.1.0]# make distclean ;make mini2440_config ; make all
生成 armboot.bin,将其烧到NandFlash 上，即可直接从NandFlash 启动，启动后3秒内没有键盘动作，则自动执行nboot 命令，
启动linux内核如下所示：
ARMboot 1.1.0 (May 23 2011 - 21:49:08)
You know that ARMboot is the ancestor of U-boot project.
Rebuilt to accommodate the MINI2440 board, by [email protected]
Feb 11 2011 ~ May 23 2011
gcc version: 2.95.3 20010315 (release)
ARMboot code: 31f00000 -> 31f168b4
DRAM Configuration:
Bank #0: 30000000 64 MB
Flash: 2 MB
*** Using default environment
Hit any key to stop autoboot: 0
Reading kernel...
Ok
Starting Linux kernel...
Uncompressing Linux.............................................................
..................................................................... done, boot
ing the kernel.
Linux version 2.6.29.4-FriendlyARM (root@russell-work-pc) (gcc version 4.3.2 (So
urcery G++ Lite 2008q3-72) ) #2 Tue Jun 9 16:26:18 CST 2009
CPU: ARM920T [41129200] revision 0 (ARMv4T), cr=c0007177
CPU: VIVT data cache, VIVT instruction cache
Machine: FriendlyARM Mini2440 development board
....
略去较长的输出信息
//////////
移植结束 生成patch：
[root@armdev arms]# diff -urNwB armboot-1.1.0 armboot-1.1.0-gk >armboot-org2mini2440.diff
/////////
小结：上面列出了ARMboot移植时候涉及到的文件及修改的位置，和修改的说明，或许直接粘贴页面上的代码难免出错误，
为方便使用，提供了如下文件包以供使用：
armboot-1.1.0.tgz ： 原始的armboot程序包
armboot-1.1.0-gk-20110523_215234.tar.gz ： 移植完成后的程序包，解开后直接编译（要有arm-linux-gcc-2.95.3的交叉编译器）
编译方法：make distclean ;make mini2440_config ; make all
armboot-org2mini2440.diff ： patch补丁包
补丁方法：将原始的armboot程序包armboot-1.1.0.tgz 解开后，将armboot-org2mini2440.diff文件放到和armboot-1.1.0的同级目录上，不要拷贝到 armboot-1.1.0 目录里面，
进到 armboot-1.1.0 执行如下的patch命令即可
patch -p1 < ../armboot-org2mini2440.diff
ARMBoot-1.1.0 在 mini2440 移植 编译后的二进制程序 可以直接烧写到Flash或下载到0x31f00000地址处运行
/////////
致谢：移植过程中使用到了若干开源代码，对这些开源代码的作者表示衷心的感谢，感谢您们的辛勤劳动和无私奉献精神！！
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