Leakage Power Optimization Techniques ------UG reading

一、Multi-Vth Optimization:

Run multi-Vth optimization only after your design meets timing.

method:

reportPower -leakage

1、optLeakagePower: This command resizes low voltage threshold gates in the design to gates with a higher voltage threshold, while maintaining timing. This command only resizes cells that have positive slack. Cells that belong to any library are candidates for swapping.

setOptMode can set the effort.

2、optDesign

setOptMode -powerEffort high/low after placeDesign

二、Substrate Biasing

Changing the body voltage of the field effect transistor (FET) affects both the threshold voltage and the static leakage current.

method:

addWellTap

For well tap cells, you must add stripes to connect the secondary power/ground pins in the vertical or horizontal direction.