marvell 内存分析
CONFIG_MV_INTERNAL_REGS_SELECTIVE_MAPPING=y
选择映射内部寄存器（分散开,每个64K），否则映射1M寄存器空间
sysmap.c文件
#if defined(CONFIG_MV_INTERNAL_REGS_SELECTIVE_MAPPING)
/* need to make sure it is big enough to hold all mapping entries */
#define MEM_TABLE_MAX_ENTRIES 30
/* default mapped entries */
#define MEM_TABLE_ENTRIES 7
/* number of entries to map */
volatile u32 entries = MEM_TABLE_ENTRIES;
struct _mv_internal_regs_map {
MV_UNIT_ID id;
u32 index;
u32 offset;
u32 size;
};
/* Internal registers mapping table */
struct _mv_internal_regs_map mv_internal_regs_map[] = {
{DRAM_UNIT_ID, 0, DRAM_BASE, SZ_64K},
{CESA_UNIT_ID, 0, MV_CESA_TDMA_REG_BASE, SZ_64K},
{USB_UNIT_ID, 0, USB_REG_BASE(0), SZ_64K},
{XOR_UNIT_ID, 0, MV_XOR_REG_BASE, SZ_64K},
{ETH_GIG_UNIT_ID, 0, MV_ETH_REG_BASE(0), SZ_8K}, /* GbE port0 registers */
{ETH_GIG_UNIT_ID, 1, MV_ETH_REG_BASE(1), SZ_8K}, /* GbE port1 registers */
{SATA_UNIT_ID, 0, (SATA_REG_BASE + 0x2000), SZ_8K }, /* SATA port0 registers */
{SATA_UNIT_ID, 1, (SATA_REG_BASE + 0x4000), SZ_8K }, /* SATA port1 registers */
{SDIO_UNIT_ID, 0, MV_SDIO_REG_BASE, SZ_64K},
{AUDIO_UNIT_ID, 0, AUDIO_REG_BASE(0), SZ_64K},
{TS_UNIT_ID, 0, TSU_GLOBAL_REG_BASE, SZ_16K},
{TDM_UNIT_ID, 0, TDM_REG_BASE, SZ_64K}
};
/* AHB to MBUS mapping entry */
struct map_desc AHB_TO_MBUS_MAP[] = {
{(INTER_REGS_BASE + MAX_AHB_TO_MBUS_REG_BASE), __phys_to_pfn(INTER_REGS_BASE + MAX_AHB_TO_MBUS_REG_BASE),
SZ_64K, MT_DEVICE},
};
/* WARNING: update of this table requires updating MEM_TABLE_ENTRIES */
struct map_desc MEM_TABLE[MEM_TABLE_MAX_ENTRIES] = {
{(INTER_REGS_BASE + MPP_REG_BASE), __phys_to_pfn(INTER_REGS_BASE + MPP_REG_BASE), SZ_64K, MT_DEVICE},
{(INTER_REGS_BASE + SATA_REG_BASE), __phys_to_pfn(INTER_REGS_BASE + SATA_REG_BASE), SZ_8K, MT_DEVICE},
{(INTER_REGS_BASE + PEX_IF_BASE(0)),__phys_to_pfn(INTER_REGS_BASE + PEX_IF_BASE(0)),SZ_64K, MT_DEVICE},
{ PEX0_IO_BASE, __phys_to_pfn(PEX0_IO_BASE), PEX0_IO_SIZE, MT_DEVICE},
{ NFLASH_CS_BASE, __phys_to_pfn(NFLASH_CS_BASE), NFLASH_CS_SIZE, MT_DEVICE},
{ SPI_CS_BASE, __phys_to_pfn(SPI_CS_BASE), SPI_CS_SIZE, MT_DEVICE},
{ CRYPT_ENG_BASE, __phys_to_pfn(CRYPT_ENG_BASE), CRYPT_ENG_SIZE, MT_DEVICE},
};
#else
struct map_desc MEM_TABLE[] = {
/* no use for pex mem remap */
/*{ PEX0_MEM_BASE, __phys_to_pfn(PEX0_MEM_BASE), PEX0_MEM_SIZE, MT_DEVICE},*/
{ INTER_REGS_BASE, __phys_to_pfn(INTER_REGS_BASE), SZ_1M, MT_DEVICE},
{ PEX0_IO_BASE, __phys_to_pfn(PEX0_IO_BASE), PEX0_IO_SIZE, MT_DEVICE},
{ NFLASH_CS_BASE, __phys_to_pfn(NFLASH_CS_BASE), NFLASH_CS_SIZE, MT_DEVICE},
{ SPI_CS_BASE, __phys_to_pfn(SPI_CS_BASE), SPI_CS_SIZE, MT_DEVICE},
{ CRYPT_ENG_BASE, __phys_to_pfn(CRYPT_ENG_BASE), CRYPT_ENG_SIZE, MT_DEVICE},
};
#endif /* CONFIG_MV_INTERNAL_REGS_SELECTIVE_MAPPING */
mvControlEnvSpec.h
#define MPP_REG_BASE 0x10000
mbus-l to mbus bridge register(需要研究，管理windowX映射的)
#define MAX_AHB_TO_MBUS_REG_BASE 0x20000
mvSysHwConfig.h
/* Internal registers: size is defined in Controllerenvironment */
#define INTER_REGS_BASE 0xF1000000
#define SPI_CS_BASE 0xf4000000
map_desc中的地址都经过mmu.c中映射