cpu之RegDst_Ins

module RegDst_Ins(
	input wire[1:0] RegDst,
	input wire[4:0] src1,
	input wire[4:0] src2,
	output reg[4:0] dst
);

always @(RegDst,src1,src2) begin
	case (RegDst) 
		2'b00 : begin
			dst<=src1;
		end
		
		2'b01 : begin
			dst<=src2;
		end
		
		2'b10 : begin
			dst<=5'b00000;
		end
		
	endcase
		
end

endmodule