fpga综合报告

  

Synplify pro 的一般步骤：导入源文件－ > 设置 xilinx 约束－ > 选择 xilinx 器件并设置必要的器件参数－ > 执行综合－ > 分析综合的结果－ > 再启动综合过程－ > 向 xilinx 提交网表和约束文件

在执行综合的之前先要对源程序进行编译，检查语法正确性以及是否满足可综合风格，即执行 run － >compile only 。在 tcl 中会给出编译的提示，包括错误警告和 notes ，编译正确后会生成三个文件，分别是日志文件 .srr ， RTL 网表 srs 和 . tlg 文件。日志文件主要由三部分组成：编译过程，映射优化的过程以及时序报告。

下面为编译过程的报告

$ Start of Compile

#Mon Apr 23 22:55:36 2007

 

Synplicity VHDL Compiler, version 3.1.0, Build 049R, built May 3 2005

Copyright (C) 1994-2005, Synplicity Inc. All Rights Reserved

 

@N:"E:/modelsim/HDL_DEMO.VHD":6:7:6:14|Top entity is set to hdl_demo.

VHDL syntax check successful!

 

Compiler output is up to date. No re-compile necessary

    下面为映射优化的过程报告

@N:"E:/modelsim/HDL_DEMO.VHD":6:7:6:14|Synthesizing work.hdl_demo.arch1

@N:"E:/modelsim/ALU.VHD":4:7:4:9|Synthesizing work.alu.arch1

Post processing for work.alu.arch1

Post processing for work.hdl_demo.arch1

@N: CL201 :"E:/modelsim/HDL_DEMO.VHD":72:3:72:4|Trying to extract state machine for register state

Extracted state machine for register state

State machine has 10 reachable states with original encodings of:

   0000

   0001

   0010

   0011

   0100

   1000

   1001

   1010

   1011

   1100

@END

    以上的报告 fsm 编译器对三个状态机的重新编码。说明了正在综合的是 work.hdl_demo.arch1 和 work.alu.arch1 综合器正视图提取 register state , 状态机按原来的编码有 10 个可达状态    0000 0001 0010 0011 0100 1000 1001 1010 1011 1100

 

Adding property syn_encoding in cell hdl_demo, value "onehot", to instance state[0:9]

 

 

@W: BN116 :"e:/modelsim/alu.vhd":19:2:19:3|Removing sequential instance outp[7:0] of view:PrimLib.dffe(prim) because there are no references to its outputs

NRtlRetiming done on outp[7:0]

RTL optimization done.

Encoding state machine work.hdl_demo(arch1)-state[0:9]

original code -> new code

   0000 -> 0000000001

   0001 -> 0000000010

   0010 -> 0000000100

   0011 -> 0000001000

   0100 -> 0000010000

   1000 -> 0000100000

   1001 -> 0001000000

   1010 -> 0010000000

   1011 -> 0100000000

   1100 -> 1000000000

以上报告表明状态机的状态被重新编码并列出了新的状态编码

Clock Buffers:

 Inserting Clock buffer for port clk,       TNM=clk

说明综合器为端口 clk 添加了一个 clock buffer ，添加 buffer 的目的是为了提高电路工作频率使之更容易满足时序的要求。

 

Timing driven replication report

@N: FX235 :"e:/modelsim/hdl_demo.vhd":51:3:51:10|Instance "alu_inst.outp_ret_24[0]" with 8 loads has been replicated 1 time(s) to improve timing

@N: FX235 :"e:/modelsim/hdl_demo.vhd":51:3:51:10|Instance "alu_inst.outp_ret_24[2]" with 8 loads has been replicated 1 time(s) to improve timing

@N: FX235 :"e:/modelsim/hdl_demo.vhd":51:3:51:10|Instance "alu_inst.outp_ret_24[1]" with 8 loads has been replicated 1 time(s) to improve timing

Added 3 Registers via timing driven replication

Added 0 LUTs via timing driven replication

报告了 net 缓冲的情况：缓冲或重复（ replication ）的 net 分段数目 为缓冲而插入的缓冲器数目，以及为了重复而添加的寄存器和 LUT 的数目。

Timing driven replication report

No replication required.

 

Timing driven replication report

No replication required.

 

Timing driven replication report

No replication required.

 

Timing driven replication report

No replication required.

一下为时序报告

Pass              CPU time           Worst Slack         Luts / Registers

------------------------------------------------------------

   1             0h:0m:1s            -0.89ns         46 /        42

   2             0h:0m:1s            -0.87ns         49 /        42

   3             0h:0m:1s            -0.87ns         49 /        42

   4             0h:0m:1s            -0.87ns         49 /        42

Timing driven replication report

No replication required.

 

   5             0h:0m:1s            -0.87ns         49 /        42

   6             0h:0m:1s            -0.87ns         49 /        42

   7             0h:0m:1s            -0.87ns         49 /        42

------------------------------------------------------------

报告了最严重的 Slack     ，为负值，说明综合后的电路的时序没有能够满足要求。

Timing driven replication report

No replication required.

 

Timing driven replication report

No replication required.

 

Pass              CPU time           Worst Slack         Luts / Registers

------------------------------------------------------------

   1             0h:0m:1s            -0.87ns         46 /        42

   2             0h:0m:1s            -0.87ns         46 /        42

   3             0h:0m:1s            -0.87ns         46 /        42

Timing driven replication report

No replication required.

 

   4             0h:0m:1s            -0.87ns         46 /        42

   5             0h:0m:1s            -0.87ns         46 /        42

   6             0h:0m:1s            -0.87ns         46 /        42

------------------------------------------------------------

 

Net buffering Report for view:work.hdl_demo(arch1):

No nets needed buffering.

 

@N: MF197 |Retiming summary : 8 registers retimed to 28

 

              ##### BEGIN RETIMING REPORT #####

 

Retiming summary : 8 registers retimed to 28

 

Original and Pipelined registers replaced by retiming :

              alu_inst.outp[0]

              alu_inst.outp[1]

              alu_inst.outp[2]

              alu_inst.outp[3]

              alu_inst.outp[4]

              alu_inst.outp[5]

              alu_inst.outp[6]

              alu_inst.outp[7]

 

New registers created by retiming :

              alu_inst.outp_ret

              alu_inst.outp_ret_24

              alu_inst.outp_ret_24_fast

              alu_inst.outp_ret_27

              alu_inst.outp_ret_34

              alu_inst.outp_ret_36

              alu_inst.outp_ret_38

              alu_inst.outp_ret_40

              alu_inst.outp_ret_42

              alu_inst.outp_ret_44

              alu_inst.outp_ret_46

 

 

              #####   END RETIMING REPORT #####

 

@N: FX164 |The option to pack flops in the IOB has not been specified

Writing Analyst data base E:/modelsim/rev_2/HDL_DEMO.srm

@N|Set autoconstraint_io

Writing EDIF Netlist and constraint files

@N|Set autoconstraint_io

@N|Set autoconstraint_io

Found clock hdl_demo|clk with period 3.33ns

 

 

##### START OF TIMING REPORT #####[

# Timing Report written on Mon Apr 23 22:55:39 2007

#

 

 

Top view:               hdl_demo

Requested Frequency:    300.0 MHz     设置的工作频率

Wire load mode:         top

Paths requested:        5      设置显示的关键路径数目

Constraint File(s):    E:/synplify/alu_syn_demo_2.sdc

                       E:/modelsim/rev_2/HDL_DEMO_fsm.sdc

                      

@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

 

@N: MT196 |Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock..

 

 

 

Performance Summary

*******************

 

 

Worst slack in design: -0.868   最严重 slack

 

                   Requested     Estimated     Requested     Estimated                Clock        Clock             

Starting Clock     Frequency     Frequency     Period        Period        Slack      Type         Group             

-------------------------------------------------------------------------------------------------------

hdl_demo|clk       300.0 MHz     238.0 MHz     3.333         4.201         -0.868     inferred     Inferred_clkgroup_0

=============================================================

 

Clocks                      |    rise to rise    |    fall to fall   |    rise to fall   |    fall to rise

-------------------------------------------------------------------------------------------------------

Starting      Ending        | constraint slack   | constraint slack | constraint slack | constraint slack

-------------------------------------------------------------------------------------------------------

hdl_demo|clk hdl_demo|clk | 3.333       -0.868  | No paths    -      | No paths    -      | No paths    -   

===================================================================================================================

 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.

       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.

 

Total path delay (propagation time + setup) of 4.201 is 3.310(78.8%) logic and 0.891(21.2%) route.

 

 

Path information for path number 5:

    Requested Period:                        3.333

    = Required time:                         3.333

 

    - Propagation time:                      4.180

    = Slack (non-critical) :                 -0.847

该路径的终点的 Required time 为 3.333 ，是通过时钟周期减去建立时间而得到的，这里的建立时间设置为 0 ，不显示。该路径的 slack 值，是通过 required time 减去传输时间再减去输入时延，传输时延为一下表中的 delay 一列的和，输入延迟这里也设置为 0 ，不显示。

报告还告知了关键路径的起点和终点以及路径的中间节点的名字和延迟 扇出

 

    Number of logic level(s):                3

    Starting point:                          alu_inst.outp_ret_24_fast[1] / Q

    Ending point:                            result[7:0] / result[3]

    The start point is clocked by            hdl_demo|clk [rising] on pin C

    The end   point is clocked by            hdl_demo|clk [rising]

 

Instance / Net                              Pin           Pin               Arrival     No. of   

Name                             Type       Name          Dir     Delay     Time        Fan Out(s)

--------------------------------------------------------------------------------------------------

alu_inst.outp_ret_24_fast[1]     FDE        Q             Out     0.370     0.370       -        

outp_ret_24_fast[1]              Net        -             -       0.506     -           6        

alu_inst.outp_6_2_1[3]           LUT4_L     I1            In      -         0.876       -        

alu_inst.outp_6_2_1[3]           LUT4_L     LO            Out     0.264     1.140       -        

outp_6_2_1[3]                    Net        -             -       0.095    -           1        

alu_inst.outp_6_2[3]             LUT4       I1            In      -         1.234       -        

alu_inst.outp_6_2[3]             LUT4       O             Out     0.264     1.498       -        

result_c[3]                      Net        -             -       0.270     -           1        

result_obuf[3]                   OBUF       I             In      -         1.768       -        

result_obuf[3]                   OBUF       O             Out     2.412     4.180       -         

result[3]                        Net        -             -       0.000     -           1        

result[7:0]                      Port       result[3]     Out     -         4.180       -        

==================================================================================================

Total path delay (propagation time + setup) of 4.180 is 3.310(79.2%) logic and 0.870(20.8%) route.

##### END OF TIMING REPORT #####]

资源占用的情况报告

---------------------------------------

Resource Usage Report for hdl_demo

 

Mapping to part: xc2vp2fg256-7

Cell usage:

FDCE            13 uses

FDE             28 uses

FDPE            1 use

MUXCY_L         7 uses

MUXF5           1 use

VCC             1 use

XORCY           8 uses

LUT2            5 uses

LUT3            11 uses

LUT4            30 uses

 

I/O primitives: 60

IBUF           52 uses

OBUF           8 uses

 

BUFGP          1 use

 

I/O Register bits:                  0

Register bits not including I/Os:   42 (1%)

 

Global Clock Buffers: 1 of 16 (6%)

 

 

Mapping Summary:

Total LUTs: 46 (1%)

 

Mapper successful!