16位rgb2gray算法verilog移植

用三级流水线

优化方法：整体扩大256倍，再右移8位

verilog代码

//==================local defines==================
`define		SIM
module	rgb2gray(
//==================System signal==================
	input					clk				,
	input					rst_n			,
//==================Interface======================
	input			[4:0]	cmos_R0			,
	input			[5:0]	cmos_G0			,
	input			[4:0]	cmos_B0			,
	output reg    	[7:0]   img_Y1			

//==================Others=========================
);
//==================Parameter======================

//==================System reg=====================
	reg     [15:0]    		cmos_R1;
	reg     [15:0]    		cmos_G1;
	reg     [15:0]    		cmos_B1;
	reg    	[15:0]    		img_Y0;

//==================System wire====================

//==================Main Code======================
//第一级
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)begin
		cmos_R1 <= 16'd0;
		cmos_G1 <= 16'd0;
		cmos_B1 <= 16'd0;
    end
    else begin
        cmos_R1 <= cmos_R0 * 8'd77;
        cmos_G1 <= cmos_G0 * 8'd150;
        cmos_B1 <= cmos_B0 * 8'd29; 
    end
end
//算Y 第二级
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)begin
        img_Y0 <= 16'd0;
    end
    else begin
        img_Y0  <= cmos_R1 + cmos_G1 + cmos_B1;
    end   
end
//delay 1clk
always @(posedge clk or negedge rst_n)
begin
    if(!rst_n)begin
        img_Y1  <= 8'd0;
    end
    else begin
        img_Y1  <= img_Y0  [15:8];
    end   
end 
endmodule