数字电路设计之低功耗设计方法三：操作数隔离

        Isolate-operand：就是在进行一些操作比如选择器的时候，我们选择的那个选项有A和B，但是如果我们直到选择的是A，那么B之前一大堆计算就显得没有必要了。所以操作数隔离也就是增加一些选择器件，如果这个操作数不需要的话就不选择它以及不进行之前计算这个操作数所需要的操作。

没使用的代码：

module isolated(
A,
B,
C,
D,
clk,
clr,
choose,
result
    );


input wire clk;
input wire clr;
input wire [1:0]choose;
input wire [31:0]A;
input wire [31:0]B;
input wire [31:0]C;
input wire [31:0]D;
output reg [31:0]result;
 
wire [31:0]choose_a;
wire [31:0]choose_b;
wire [31:0]choose_c;
wire [31:0]choose_d;


//这是一个简单的mux，先计算出A，B，C，D的值再选择
  
assign choose_a = A*B;
assign choose_b = A+B+C+D;
assign choose_c = B*C;
assign choose_d = C*D;
 
always@(posedge clk,posedge clr)
begin
   if(clr)
 result <= 0;
else
  begin
  if(choose == 2'b00)
  result <= choose_a;
else if(choose == 2'b01)
  result <= choose_b;
else if(choose == 2'b10)
  result <= choose_c;
else
  result <= choose_d;
end
end

endmodule

使用后的代码：

module isolated2(
A,
B,
C,
D,
clk,
clr,
choose,
result
    );


input wire clk;
input wire clr;
input wire [1:0]choose;
input wire [31:0]A;
input wire [31:0]B;
input wire [31:0]C;
input wire [31:0]D;
output reg [31:0]result;
 
reg [31:0]choose_A;
reg [31:0]choose_B;
reg [31:0]choose_C;
reg [31:0]choose_D;
reg [1:0]cho;
//这是一个使用了isolated的mux，先根据信号然后相应计算所需的A，B，C或者D的值


always@(posedge clk,posedge clr)
begin
   if(clr)
  begin
         choose_A <= 0;
         choose_B <= 0;
         choose_C <= 0;
         choose_D <= 0;
cho      <= 0;
end
else 
if(choose == 2'b00)
  begin
         choose_A <= A;
         choose_B <= B;
         choose_C <= choose_C;
         choose_D <= choose_D; 
 cho      <= 0;
  end
else if(choose == 2'b01)
  begin
         choose_A <= A;
         choose_B <= B;
         choose_C <= C;
         choose_D <= D;  
         cho      <= 1;
  end
else if(choose == 2'b10)
  begin
         choose_A <= choose_A;
         choose_B <= B;
         choose_C <= C;
         choose_D <= choose_D;  
         cho      <= 2;
  end
else
  begin
         choose_A <= choose_A;
         choose_B <= choose_B;
         choose_C <= C;
         choose_D <= D;  
         cho      <= 3;
  end
end


always@(posedge clk,posedge clr)
begin
   if(clr)
 result <= 0;
else 
  begin
  if(cho == 2'b00)
  result <= choose_A*choose_B;
else if(cho == 2'b01)
   result <= choose_A+choose_B+choose_C+choose_D;
else if(cho == 2'b10)
    result <= choose_B*choose_C;
   else
    result <= choose_C*choose_D;
end
end


endmodule

仿真代码：

module test;

// Inputs
reg [31:0] A;
reg [31:0] B;
reg [31:0] C;
reg [31:0] D;
reg clk;
reg clr;
reg [1:0] choose;


// Outputs
wire [31:0] result;


// Instantiate the Unit Under Test (UUT)
isolated uut (
.A(A), 
.B(B), 
.C(C), 
.D(D), 
.clk(clk), 
.clr(clr), 
.choose(choose), 
.result(result)
);


      always #50
  clk = ~clk;


      initial begin
      $dumpfile("isolated.vcd");
      $dumpvars(1,test.uut);

// Initialize Inputs
A = 0;
B = 0;
C = 0;
D = 0;
clk = 0;
clr = 1;
choose = 0;
 
 
// Wait 100 ns for global reset to finish
#100;
clr = 0; 
// Add stimulus here
#100;
A = 32'h1;
B = 32'hfff1;
choose = 0;
#100;
B = 32'h1111;
C = 32'hf;
choose = 2;
#100;
D = 32'h1234;
choose = 1;
#100;
D = 32'h1234;
choose = 2;
#100;
A = 32'hffff;
B = 32'h1212;
choose = 3;
#100;
C = 32'hffff;
D = 32'h1212;
choose = 3;
#100;
A = 32'h1;
B = 32'hfff1;
choose = 2;
#100;
B = 32'h1111;
C = 32'hf;
choose = 0;
#100;
D = 32'h1234;
choose = 3;
  end
      
endmodule