开平方的verilog代码
目录
1.逐次逼近算法描述
2.Verilog实现
3.Testbench编写
1.逐次逼近算法描述
逐次逼近算法流程如图 1所示，首先数据输入data[7:0]，接着设置实验值D_z[3:0]和确定值D_q[3:0]，然后按照从高往低的顺序，依次将每一位置1（如D_z[3]置1），再将实验值平方后与输入数据比较，若实验值的平方大于输入值(D_z^2 > data)，则此位为0（D_q[3]为0），反之（(D_z^2 ≤ data)），此位为1（D_q[3]为1）；以此迭代到最后一位。
可见，如果是n bit的数据，那么需要n/2次迭代，每次计算如果一个周期，则需要n/2个周期。
图 1逐次逼近算法框图
2.Verilog实现
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//////////////////////////////////////////////////////////////////////////////////
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//
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// 逐次逼近算法
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//
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module sqrt_1
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#(
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parameter d_width = 8,
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parameter q_width = d_width/2 - 1,
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parameter r_width = q_width + 1 )
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(
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input wire clk,
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input wire rst,
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input wire i_vaild,
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input wire [d_width:0] data_i, //输入
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-
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output reg o_vaild,
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output reg [q_width:0] data_o, //输出
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output reg [r_width:0] data_r //余数
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);
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//--------------------------------------------------------------------------------
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reg [d_width:0] D [r_width:1]; //被开方数
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reg [q_width:0] Q_z [r_width:1]; //临时
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reg [q_width:0] Q_q [r_width:1]; //确认
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reg ivalid_t [r_width:1];
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//--------------------------------------------------------------------------------
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always@(posedge clk or posedge rst)
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begin
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if(rst)
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begin
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D[r_width]
<= 0;
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Q_z[r_width] <= 0;
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Q_q[r_width] <= 0;
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ivalid_t[r_width] <= 0;
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end
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else if(i_vaild)
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begin
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D[r_width] <= data_i; //被开方数据
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Q_z[r_width] <= {1'b1,{q_width{1'b0}}}; //实验值设置
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Q_q[r_width] <= 0; //实际计算结果
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ivalid_t[r_width] <= 1;
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end
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else
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begin
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D[r_width] <= 0;
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Q_z[r_width] <= 0;
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Q_q[r_width] <= 0;
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ivalid_t[r_width] <= 0;
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end
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end
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//-------------------------------------------------------------------------------
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// 迭代计算过程
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//-------------------------------------------------------------------------------
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generate
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genvar i;
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for(i=r_width-1;i>=1;i=i-1)
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begin:U
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always@(posedge clk or posedge rst)
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begin
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if(rst)
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begin
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D[i]
<= 0;
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Q_z[
i] <=
0;
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Q_q[
i] <=
0;
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ivalid_t[
i] <=
0;
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end
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else
if(
ivalid_t[
i+
1])
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begin
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if(
Q_z[
i+
1]*
Q_z[
i+
1] > D[i+1])
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begin
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Q_z[i]
<= {Q_q[i+1][q_width:i],1'b1,{{i-1}{1'b0}}};
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Q_q[i] <= Q_q[i+1];
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end
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else
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begin
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Q_z[i] <= {Q_z[i+1][q_width:i],1'b1,{{i-1}{1'b0}}};
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Q_q[i] <= Q_z[i+1];
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end
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D[i] <= D[i+1];
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ivalid_t[i] <= 1;
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end
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else
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begin
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ivalid_t[i] <= 0;
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D[i] <= 0;
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Q_q[i] <= 0;
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Q_z[i] <= 0;
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end
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end
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end
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endgenerate
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//--------------------------------------------------------------------------------
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// 计算余数与最终平方根
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//--------------------------------------------------------------------------------
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always@(posedge clk or posedge rst)
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begin
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if(rst)
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begin
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data_o <= 0;
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data_r <= 0;
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o_vaild <= 0;
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end
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else if(ivalid_t[1])
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begin
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if(Q_z[1]*Q_z[1] > D[1])
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begin
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data_o
<= Q_q[1];
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data_r <=
D[1]
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Q_q[
1]*
Q_q[
1];
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o_vaild <=
1;
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end
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else
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begin
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data_o <=
{Q_q[1][q_width:1],Q_z[1][0]};
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data_r <=
D[1]
- {
Q_q[
1][
q_width:1],
Q_z[
1][
0]}*{
Q_q[
1][
q_width:1],
Q_z[
1][
0]};
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o_vaild <=
1;
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end
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end
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else
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begin
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data_o <=
0;
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data_r <=
0;
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o_vaild <=
0;
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end
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end
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//
--------------------------------------------------------------------------------
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3.Testbench编写
//--------------------------------------------------------------------------------
`define d_w 8
`define q_w `d_w / 2
`define r_w `q_w + 1
//--------------------------------------------------------------------------------
module tb_sqrt;
//--------------------------------------------------------------------------------
// Inputs
reg clk;
reg rst;
reg i_vaild;
reg [`d_w-1:0] data_i;
// Outputs
wire o_vaild;
wire [`q_w-1:0] data_o;
wire [`r_w-1:0] data_r;
//--------------------------------------------------------------------------------
// Instantiate the Unit Under Test (UUT)
sqrt_1
#(
.d_width ( `d_w-1 ),
.q_width ( `q_w-1 ),
.r_width ( `r_w-1 )
)
uut
(
.clk ( clk ),
.rst ( rst ),
.i_vaild ( i_vaild ),
.data_i ( data_i ),
.o_vaild ( o_vaild ),
.data_o ( data_o ),
.data_r ( data_r )
);
//--------------------------------------------------------------------------------
initial begin
// Initialize Inputs
clk = 0;
rst = 1;
// Wait 100 ns for global reset to finish
#100;
rst = 0;
// Add stimulus here
end
always #5 clk = ~ clk ;
reg [`d_w:0] cnt ;
reg [31:0] a ;
//--------------------------------------------------------------------------------
always@(posedge clk or posedge rst)
begin
if(rst)
begin
i_vaild <= 0;
data_i <= 0;
cnt <= 0;
end
else if(cnt < 10)
begin
i_vaild <= 1;
data_i <= {$random} % 255;
cnt <= cnt + 1;
end
else
begin
i_vaild <= 0;
data_i <= 0;
cnt <= cnt;
end
end
//--------------------------------------------------------------------------------
endmodule
用语句 data_i <= {$random} % 255; 产生一个0~255的随机数进行测试。
仿真结果如图 2所示，计算周期为4个时钟周期，输入数据data_i，开方结果data_o，余数data_r。
图 2 仿真结果