用FPGA实现8'bitSRAM读写控制的Verilog代码

`define SRAM_SIZE 8
`timescale 1ns/1ns
//FOR SRAM INTERFACE CONTROL
module SRAM_INTERFACE(in_data,//INPUT DATA
            out_data,//OUTPUT DATA
            fiford,//FIFO READ CONTROL LOW VOLTAGE
            fifowr,//FIFO WRITE CONTROL LOW VOLTAGE
            nfull,
            nempty,
            address,//SENT SRAM ADDRESS BUS
            sram_data,//SRAM DATA BUS
            rd,//SRAM READ SINGAL ENABLE LOW VOLTAGE
            wr,//SRAM WRITE ENABLE LOW VOLTAGE
            clk,//system clk
            rst);//global reset singal,low voltage
input  fiford,fifowr,clk,rst;
input[7:0] in_data;
output[7:0] out_data;
reg[7:0]  in_data_buf,out_data_buf;//input and output buffer
output  reg  nfull,nempty;
output rd,wr;
inout[7:0] sram_data;
output reg [10:0]address;
reg[10:0] fifo_wp,fifo_rp;
reg[10:0]fifo_wp_next,fifo_rp_next;
reg near_full,near_empty;
reg[3:0] state;

parameter idle=4'b0000,
          read_ready='b0100,
          read='b0101,
          read_over='b0111,
          write_ready='b1000,
          write='b1001,
          write_over='b1011;

always@(posedge clk or negedge rst)
begin
      if(!rst)
          state<=idle;
       else case(state)
               idle:begin
                    if(fifowr==0&&nfull)
                     state<=write_ready;
                   else if(fiford==0&&nempty)
                     state<=read_ready;
                   else
                     state<=idle;
                    end
               read_ready:
                     state<=read;
               read:begin
                     if(fiford==1)
                        state<=read_over;
                      else
                        state<=read;
                    end
               read_over:
                       state<=idle;
               write_ready:
                       state<=write;
               write:begin
                     if(fifowr==1)
                        state<=write_over;
                      else
                       state<=write;
                      end
               write_over:
                        state<=idle;
              default:state<=idle;
               endcase
end

assign rd=~state[2];
assign wr=(state==write)?fifowr:1'b1;

always@(posedge clk)
begin
          if(~fifowr)
                 in_data_buf<=in_data;
end
//=============================================================
always@(state or fiford or fifowr or fifo_wp or fifo_rp)
begin
     if(state[2]||~fiford)
          address=fifo_rp;
     else if(state[3]||~fifowr)
          address=fifo_wp; 
     else
          address='bz;
end
//=================================================================
assign out_data=(state[2])?sram_data:8'bz;
always@(posedge clk)
begin
     if(state==read)
         out_data_buf<=sram_data;
end
//==================================================
always@(posedge clk or negedge rst)
begin
      if(!rst)
           fifo_rp<=0;
      else if(state==read_over)
           fifo_rp<=fifo_rp_next;
end
//===================================================
always@(fifo_rp)
begin
      if(fifo_rp==`SRAM_SIZE-1)
            fifo_rp_next=0;
      else
            fifo_rp_next=fifo_rp+1;
end
//=====================================================
always@(posedge clk or negedge rst)
begin
  if(!rst)
         fifo_wp<=0;
   else if(state==write_over)
         fifo_wp<=fifo_wp_next;
end
//==================================================
always@(fifo_wp)
begin
      if(fifo_wp==`SRAM_SIZE-1)
            fifo_wp_next=0;
      else
            fifo_wp_next=fifo_wp+1;
end
//===================================================
always@(posedge clk or negedge rst)
begin
  if(!rst)
       near_empty<=1'b0;
  else if(fifo_wp==fifo_rp_next)
       near_empty<=1'b1;
  else
       near_empty<=1'b0;
end
//=======================================================
always@(posedge clk or negedge rst)
begin
      if(!rst)
     nempty<=1'b0;
      else if(near_empty&&state==read)
      nempty<=1'b0;
      else if(state==write)
      nempty<=1'b1;
end
//======================================================
always@(posedge clk or negedge rst)
begin
  if(!rst)
       near_full<=1'b0;
  else if(fifo_rp==fifo_wp_next)
       near_full<=1'b1;
  else
       near_full<=1'b0;
end
//====================================================
always@(posedge clk or negedge rst)
begin
      if(!rst)
     nfull<=1'b1;
      else if(near_full&&state==write)
      nfull<=1'b0;
      else if(state==read)
      nfull<=1'b1;
end
//===========================================================
endmodule