4x8段数码管verilog代码

调试代码OK，准备做成avalon总线的ip核

 

// --------------------------------------------------------------------
// Copyright (c) 2010 by XuX.
// --------------------------------------------------------------------
//          
//                     XuX.
//                     web: http://blog.csdn.net/xuxin813
//                     email: [email protected]
//
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//
// Major Functions: XuX2C8 Board TOP LEVEL
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :|    Changes Made:
//   V1.0 :| Mercury         :| 2010/10/19:|       Initial Revision
// --------------------------------------------------------------------

module Delay(iRST,iCLK,oCLK10ms);
input  iRST;
input  iCLK;

output reg oCLK10ms;
reg [27:0] Cont;

always@(posedge iCLK or negedge iRST)
begin
 if(!iRST)
 begin
  Cont <= 28'h0000000;
  oCLK10ms <= 0;
 end
 else
 begin
  if(Cont < 28'h000f080)  
  begin
   Cont <= Cont+1;
  end
  else
  begin
   oCLK10ms <= ~oCLK10ms;
   Cont <= 28'h0000000;
   end
 end
end

endmodule

module xuxLed4x8
(
 Clk,
 Rst,
  
 Led4x8_dat_o,       // 4x8 led data
 Led4x8_sel_o,       // 4x8 led select
  
 Data_i 
);

input Clk;
input Rst;

input  [31:0]  Data_i;

output  [7:0]  Led4x8_dat_o;
output  [3:0]  Led4x8_sel_o;

reg   [7:0]  Led4x8_dat_o;
reg    [3:0]  Led4x8_sel_o;

wire   clk_25ms;

Delay Delay(
 .iRST(Rst),
 .iCLK(Clk),
 .oCLK10ms(clk_25ms)
 );

always @ (negedge clk_25ms or negedge Rst)
begin
 
 if (!Rst)
 begin
  Led4x8_dat_o <= 8'h00;
  Led4x8_sel_o <= 4'b0001;
 end

  else
    begin
         
     case(Led4x8_sel_o)
      4'b1000: 
      begin
     Led4x8_dat_o <= Data_i[31:24];
     Led4x8_sel_o <= 4'b0001;
    end
      4'b0001: 
      begin
     Led4x8_dat_o <= Data_i[23:16];
     Led4x8_sel_o <= 4'b0010;
    end
      4'b0010: 
    begin
     Led4x8_dat_o <= Data_i[15:8];
     Led4x8_sel_o <= 4'b0100;
    end
      4'b0100: 
      begin
     Led4x8_dat_o <= Data_i[7:0];
     Led4x8_sel_o <= 4'b1000;
    end
    default:
     Led4x8_sel_o <= 4'b0001;
     endcase
    end
 

end

endmodule