Verilog专题（二十三）Lemmings2

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题目

In addition to walking left and right, Lemmings will fall (and presumably go "aaah!") if the ground disappears underneath them.

In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say "aaah!". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.

Build a finite state machine that models this behaviour.

 

Module Declaration

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah );

状态转移图

 

我的设计

    根据题意，left和right的移动和上一题一样，但是除了在向左和向右行走以及在颠簸时改变方向外，当ground= 0时，旅鼠也会掉下来并说“ aaah！”。当地面重新出现时（ground= 1），旅鼠将恢复与跌倒之前相同的方向行走。跌倒时被撞击不会影响步行方向，并且与地面消失（但尚未坠落）的周期相同，或者当地面仍在坠落时重新出现时，也不会影响步行方向。代码如下：

module top_module(    input clk,    input areset,    // Freshly brainwashed Lemmings walk left.    input bump_left,    input bump_right,    input ground,    output walk_left,    output walk_right,    output aaah );​    localparam left = 0;    localparam right = 1;    localparam fall_l = 2;    localparam fall_r = 3;        reg[1:0] state, next_state;    reg[2:0] out;        //state    always@(posedge clk or posedge areset) begin        if(areset)            state <= left;        else            state <= next_state;    end        //transition    always@(*)begin        case(state)            left:next_state=ground?(bump_left?right:left):fall_l;            right:next_state=ground?(bump_right?left:right):fall_r;            fall_l:next_state=ground?left:fall_l;            fall_r:next_state=ground?right:fall_r;        endcase    end        //out    always@(posedge clk or posedge areset) begin        if(areset)            out <= 3'b100;        else            case(next_state)                left: out <= 3'b100;                fall_l: out <= 3'b001;                right: out <= 3'b010;                fall_r: out <= 3'b001;            endcase    end        assign {walk_left, walk_right, aaah} = out;    endmodule

 

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