AXI接口的MIG测试【MIZ7035学习】
1.前言
刚买了米联客的MIZ7035开发板，这几天休假也不出去，就在家拿回来测一些东西。
主要目的是学习：
- PL端的DDR3接口
- GTX用作PCIE接口
- SFP接口
- HDMI接口
- SD卡和eMMC共存情况下的PetaLinux
主要就是这些了。过程主要是自己根据原理图、文档在Vivado上直接新建工程来进行测试，米联客的资料作为辅助，需要时进行查看。
这次先来测试MIG做出的DDR3控制器，看看效果怎么样。
2.新建Vivado工程
新建工程，点击Next
选择FPGA型号
点击Next，Finish
新建BD,点击OK
3.AXI接口的MIG IP
点击Add IP，添加MIG IP
双击MIG IP的GUI,
弹出窗口Xilinx Memory Interface Generator，
点击Next
默认新建设计，1个控制器，AXI4接口
点击Next
选择DDR3 SDRAM
默认设置800MHz时钟，然后修改Memory Part为MT41K256M16XX-125，Data Width选择32位，其他设置默认
AXI的Data Width选择64位和PS的HP接口对应或者32位和GP接口对应，地址线读写仲裁选择ROUND_ROBIN，其他默认
因为刚才选了800MHz和4:1，所以这里的输入时钟选择200MHz，其他默认
系统时钟和参考时钟来源于FPGA内部，这里选择No Buffer，其他默认
内部终端电阻选择50欧
板子已经是现成的选择Fixed Pin Out
参照原理图，填写所有引脚的信息，然后点Validate验证。或者直接读取创建好的UCF文件。
UCF内容：
NET "ddr3_dq[0]" LOC = "G1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[1]" LOC = "J4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[2]" LOC = "H1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[3]" LOC = "H4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[4]" LOC = "H2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[5]" LOC = "L3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[6]" LOC = "J1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[7]" LOC = "K3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[8]" LOC = "F3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[9]" LOC = "C1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[10]" LOC = "E2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[11]" LOC = "D3" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[12]" LOC = "G4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[13]" LOC = "D1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[14]" LOC = "E1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[15]" LOC = "F4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[16]" LOC = "M1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[17]" LOC = "L5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[18]" LOC = "M4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[19]" LOC = "M5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[20]" LOC = "M2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[21]" LOC = "N4" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[22]" LOC = "L2" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[23]" LOC = "N1" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[24]" LOC = "K6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[25]" LOC = "K7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[26]" LOC = "N7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[27]" LOC = "J5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[28]" LOC = "M7" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[29]" LOC = "K8" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[30]" LOC = "N6" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dq[31]" LOC = "K5" | IOSTANDARD = SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dm[0]" LOC = "H3" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dm[1]" LOC = "D4" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dm[2]" LOC = "M6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dm[3]" LOC = "J6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[0]" LOC = "K2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[0]" LOC = "K1" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[1]" LOC = "G2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[1]" LOC = "F2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[2]" LOC = "N3" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[2]" LOC = "N2" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_p[3]" LOC = "M8" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_dqs_n[3]" LOC = "L8" | IOSTANDARD = DIFF_SSTL15_T_DCI | VCCAUX_IO = HIGH ;
NET "ddr3_addr[14]" LOC = "D6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[13]" LOC = "B1" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[12]" LOC = "D8" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[11]" LOC = "D5" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[10]" LOC = "F8" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[9]" LOC = "C2" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[8]" LOC = "G7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[7]" LOC = "A2" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[6]" LOC = "E6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[5]" LOC = "A4" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[4]" LOC = "E5" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[3]" LOC = "B4" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[2]" LOC = "C4" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[1]" LOC = "F5" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_addr[0]" LOC = "B5" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ba[2]" LOC = "C6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ba[1]" LOC = "E7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ba[0]" LOC = "A7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ck_p[0]" LOC = "F9" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ck_n[0]" LOC = "E8" | IOSTANDARD = DIFF_SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_ras_n" LOC = "C7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_cas_n" LOC = "B7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_we_n" LOC = "B6" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_reset_n" LOC = "B2" | IOSTANDARD = LVCMOS15 | VCCAUX_IO = HIGH ;
NET "ddr3_cke[0]" LOC = "F7" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_odt[0]" LOC = "A3" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
NET "ddr3_cs_n[0]" LOC = "A5" | IOSTANDARD = SSTL15 | VCCAUX_IO = HIGH ;
默认配置
Summary，检查一下，然后下一步。
点击Accept
点击Next
点击Generate
4.PS
新建PS
双击PS7的IP
先应用一个开发板的配置(ZedBoard)，这样配置起来比较快
配置MIO
- BANk0为3.3V，BANK1为1.8V
检查各个外设是否与MIZ7035的核心板匹配 - QSPI Flash，匹配
- 以太网，匹配
- USB，匹配
- SD卡，WP信号其实没有用处，去掉，其他地方匹配
- eMMC,需要添加SD1接口，CD和WP信号无用，不需要添加
- 调试串口，匹配
- 外设复位，ENET上电复位；USB复位在PL上，而这里只能选PS的MIO引脚，所以忽略；没有I2C，取消掉。
- 其他默认
配置时钟
- 输入时钟为33.333MHZ，匹配
- CPU频率改为666.666666MHz,DDR为533.333333MHz
- 其他默认
DDR配置
- Memory Part选择MT41K256M16 RE-125
- DQS to Clock Delay全部写0
- Board Delay全部写0.25
中断配置
- 打开PL-PS的IRQ_F2P的中断功能
保存
5.Block Design
点击Run Block Automation建立PS的接口
创建Clocking Wizard
双击IP进行配置，外部GCLK的100MHz时钟，因为直接接入了时钟引脚，选择Global Buffer。
因为PL DDR3的参考时钟配置的是200MHz，这里让MMCM输出200MHz，并将Reset设置为低有效。
对端口进行连接
点击Run Connection Automation进行连接，
时钟选择/mmcm_mig7/clk_out1(200MHz)。
重新进行连线
新建IO约束文件MIZ7035_IO.xdc
写约束：
create_clock -name clk100m_i -period 10.00 [get_ports clk100m_i]
set_property VCCAUX_IO DONTCARE [get_ports clk100m_i]
set_property IOSTANDARD SSTL15 [get_ports clk100m_i]
set_property PACKAGE_PIN C8 [get_ports clk100m_i]
set_property PACKAGE_PIN H7 [get_ports rst_key]
set_property IOSTANDARD SSTL15 [get_ports rst_key]
set_property PACKAGE_PIN K10 [get_ports init_calib_complete]
set_property IOSTANDARD SSTL15 [get_ports init_calib_complete]
右键点击BD,Create HDL Wrapper,
Generate Output Products
点击Generate Bitstream完成综合、实现和生成bit。
可以查看实现结果，MIG还是占用了挺多资源的
6.SDK测试
切换到Block Design
File->Export->Export Hardware
勾选Include Bitstream
File->Launch SDK
打开SDK，自动生成了hw文件夹
File->New->Application Project
新建测试ps dram的工程
选择Zynq DRAM test
自动生成了bsp和程序的工程
Xilinx->Program FPGA
点击Program
然后右键点击工程目录，选择
Run As->Launch on Hardware
下载程序后通过串口即可对PS的DDR进行测试。
File->New->Application Project
新建测试pl dram的工程
选择Memory Tests例程
编译，下载FPGA的bit和程序的elf
即可看到对板上Memory的测试，包括了
PL的MIG控制的DDR,PS部分的DDR，以及OCM的RAM
7.总结
通过测试，挂在GP0端口上的1GB PL DDR3是可以进行访问的，因为GP0使用的是200MHz总线，而且用到的是AXI4 Lite接口，所以速度比较慢。但是应该可以用来做视频处理了。800MHz时钟，相当于1600MHz的DDR3访问速度，应该是比PS端1066MHz的DDR3存取速度要快很多的。