VHDL_LIB之DFF

 

1　　D-Flip-Flop with async reset or set

 1 library IEEE;

 2 use ieee.std_logic_1164.all;

 3 

 4 entity FFD is

 5     generic

 6     (

 7         ResetVal    : std_logic := '0';        --! select async set / async reset

 8         ClockFall   : boolean := False         --! select clock edge

 9     );

10     port

11     (

12         RST  :    in    std_logic;             　--! Async Reset

13         C    :    in    std_logic;               --! Clock

14         D    :    in    std_logic;               --! Input

15         Q    :    out    std_logic               --! Output

16     );

17 end FFD;

18 

19 architecture beh of FFD is

20     signal clock : std_logic;                    --! active clock

21 

22 begin

23 

24 gckr: if ClockFall = false generate

25     clock <= C;

26 end generate;

27 gckf: if ClockFall = true generate

28     clock <= not(C);

29 end generate;

30 

31 pFF:    process(RST,clock)

32         begin

33             if(RST = '1') then

34                 Q <= ResetVal;

35             else

36                 if(clock'Event and clock = '1') then

37                     Q    <=    D;

38                 end if;

39             end if;

40         end process pFF;

41 end beh;

  

2　　D-Flip-Flop with clock enable

1 -- Port declaration

2 CE    :    in    std_logic;           --! Clock enable

3 

4 -- Clock event

5     if(clock'Event and clock = '1') then

6         if (CE = '1') then　　Q <= D; 

7         end if;        

8     end if;