用vhdl语言实现寄存器

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

entity exprience1 is
    Port ( cs : in std_logic;
           wr : in std_logic;
           rd : in std_logic;
           data : inout std_logic_vector(3 downto 0)
             --signal tmp: inout std_logic_vector(3 downto 0));
            );
end exprience1;

architecture Behavioral of exprience1 is
signal tmp: std_logic_vector(3 downto 0);
begin
reg:process(cs, wr, rd)

begin
    if(cs = '1' and wr = '1') then
        tmp <= data;
    elsif(cs = '1' and rd = '1') then
        data <= tmp;
     else data <= "ZZZZ";
    end if;

end process reg;
end Behavioral;