如何將CMOS彩色影像轉換成灰階影像? (SOC) (DE2)
Abstract
在友晶科技的DE2_CCD範例中，CMOS所擷取的是彩色RGB影像，然後由VGA顯示出來，若我要的是灰階影像，該怎麼做呢?
Introduction
版權聲明：本文根據友晶科技光碟所附的範例程式加以修改，原範例版權歸友晶科技所有。
使用環境：Quartus II 7.2 SP3 + DE2(Cyclone II EP2C35F627C6) + TRDB_DC
本文所提的方法並不是最好的方法，建議參考新作(原創) 如何Real Time產生灰階影像? (SOC) (DE2) (TRDB-DC2)與(原創) 如何Real Time產生灰階影像? (SOC) (DE2-70) (TRDB-D5M)
在友晶科技的範例程式光碟中的DE2_CCD，展示了130萬像素CMOS基本free run與capture的功能，最後影像呈現在VGA上，其架構如下所示：
SDRAM做為VGA Controller的frame buffer，最後由VGA Controller輸出RGB影像。由於SDRAM存放的是RGB彩色資料，為了讓產生它灰階輸出，我在VGA Controller和SDRAM Controller多加了一個RGB2Gray做轉換。
RGB2Gray.v / Verilog
1
/*
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : RGB2Gray.v
5 Compiler : Quartus II 7.2 SP3
6 Description : RGB to gray
7 Release : 07/14/2008 1.0
8 */
9
10 module RGB2Gray (
11 input clk,
12 input rst_n,
13 input [ 9 : 0 ] i_r,
14 input [ 9 : 0 ] i_g,
15 input [ 9 : 0 ] i_b,
16 output reg [ 9 : 0 ] o_r,
17 output reg [ 9 : 0 ] o_g,
18 output reg [ 9 : 0 ] o_b
19 );
20
21 always@(posedge clk or negedge rst_n) begin
22 if ( ! rst_n) begin
23 o_r <= { 10 { 1 ' b0}};
24 o_g <= { 10 { 1 ' b0}};
25 o_b <= { 10 { 1 ' b0}};
26 end
27 else begin
28 o_r <= (i_r + i_g + i_b) / 3 ;
29 o_g <= (i_r + i_g + i_b) / 3 ;
30 o_b <= (i_r + i_g + i_b) / 3 ;
31 end
32 end
33
34 endmodule
2 (C) OOMusou 2008 http://oomusou.cnblogs.com
3
4 Filename : RGB2Gray.v
5 Compiler : Quartus II 7.2 SP3
6 Description : RGB to gray
7 Release : 07/14/2008 1.0
8 */
9
10 module RGB2Gray (
11 input clk,
12 input rst_n,
13 input [ 9 : 0 ] i_r,
14 input [ 9 : 0 ] i_g,
15 input [ 9 : 0 ] i_b,
16 output reg [ 9 : 0 ] o_r,
17 output reg [ 9 : 0 ] o_g,
18 output reg [ 9 : 0 ] o_b
19 );
20
21 always@(posedge clk or negedge rst_n) begin
22 if ( ! rst_n) begin
23 o_r <= { 10 { 1 ' b0}};
24 o_g <= { 10 { 1 ' b0}};
25 o_b <= { 10 { 1 ' b0}};
26 end
27 else begin
28 o_r <= (i_r + i_g + i_b) / 3 ;
29 o_g <= (i_r + i_g + i_b) / 3 ;
30 o_b <= (i_r + i_g + i_b) / 3 ;
31 end
32 end
33
34 endmodule
28行
o_r
<=
(i_r
+
i_g
+
i_b)
/
3
;
o_g <= (i_r + i_g + i_b) / 3 ;
o_b <= (i_r + i_g + i_b) / 3 ;
o_g <= (i_r + i_g + i_b) / 3 ;
o_b <= (i_r + i_g + i_b) / 3 ;
整個關鍵的演算法在此， 我只是簡單的將RGB三個加起來除以三而已，雖然不是最嚴謹的方式，但大體上以此為基礎的灰階影像，都能夠順利的做些影像演算法。
DE2_CCD.v / Verilog (DE2_CCD的top module)
1
//
--------------------------------------------------------------------
2 // Copyright (c) 2005 by Terasic Technologies Inc.
3 // --------------------------------------------------------------------
4 //
5 // Permission:
6 //
7 // Terasic grants permission to use and modify this code for use
8 // in synthesis for all Terasic Development Boards and Altera Development
9 // Kits made by Terasic. Other use of this code, including the selling
10 // ,duplication, or modification of any portion is strictly prohibited.
11 //
12 // Disclaimer:
13 //
14 // This VHDL/Verilog or C/C++ source code is intended as a design reference
15 // which illustrates how these types of functions can be implemented.
16 // It is the user's responsibility to verify their design for
17 // consistency and functionality through the use of formal
18 // verification methods. Terasic provides no warranty regarding the use
19 // or functionality of this code.
20 //
21 // --------------------------------------------------------------------
22 //
23 // Terasic Technologies Inc
24 // 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
25 // HsinChu County, Taiwan
26 // 302
27 //
28 // web: http://www.terasic.com/
29 // email: [email protected]
30 //
31 // --------------------------------------------------------------------
32 //
33 // Major Functions: DE2 CMOS Camera Demo
34 //
35 // --------------------------------------------------------------------
36 //
37 // Revision History :
38 // --------------------------------------------------------------------
39 // Ver :| Author :| Mod. Date :| Changes Made:
40 // V1.0 :| Johnny Chen :| 06/01/06 :| Initial Revision
41 // V1.1 :| Johnny Chen :| 06/02/06 :| Modify Image Quality
42 // V1.2 :| Johnny Chen :| 06/03/22 :| Change Pin Assignment For New Sensor
43 // V1.3 :| Johnny Chen :| 06/03/22 :| Fixed to Compatible with Quartus II 6.0
44 // --------------------------------------------------------------------
45
46 module DE2_CCD (
47 ////////////////// // Clock Input ////////////////// //
48 CLOCK_27, // 27 MHz
49 CLOCK_50, // 50 MHz
50 EXT_CLOCK, // External Clock
51 ////////////////// // Push Button ////////////////// //
52 KEY, // Pushbutton[3:0]
53 ////////////////// // DPDT Switch ////////////////// //
54 SW, // Toggle Switch[17:0]
55 ////////////////// // 7-SEG Dispaly ////////////////// //
56 HEX0, // Seven Segment Digit 0
57 HEX1, // Seven Segment Digit 1
58 HEX2, // Seven Segment Digit 2
59 HEX3, // Seven Segment Digit 3
60 HEX4, // Seven Segment Digit 4
61 HEX5, // Seven Segment Digit 5
62 HEX6, // Seven Segment Digit 6
63 HEX7, // Seven Segment Digit 7
64 //////////////////////// LED ////////////////////////
65 LEDG, // LED Green[8:0]
66 LEDR, // LED Red[17:0]
67 //////////////////////// UART ////////////////////////
68 UART_TXD, // UART Transmitter
69 UART_RXD, // UART Receiver
70 //////////////////////// IRDA ////////////////////////
71 IRDA_TXD, // IRDA Transmitter
72 IRDA_RXD, // IRDA Receiver
73 ///////////////////// SDRAM Interface /////////////// /
74 DRAM_DQ, // SDRAM Data bus 16 Bits
75 DRAM_ADDR, // SDRAM Address bus 12 Bits
76 DRAM_LDQM, // SDRAM Low-byte Data Mask
77 DRAM_UDQM, // SDRAM High-byte Data Mask
78 DRAM_WE_N, // SDRAM Write Enable
79 DRAM_CAS_N, // SDRAM Column Address Strobe
80 DRAM_RAS_N, // SDRAM Row Address Strobe
81 DRAM_CS_N, // SDRAM Chip Select
82 DRAM_BA_0, // SDRAM Bank Address 0
83 DRAM_BA_1, // SDRAM Bank Address 0
84 DRAM_CLK, // SDRAM Clock
85 DRAM_CKE, // SDRAM Clock Enable
86 ////////////////// // Flash Interface /////////////// /
87 FL_DQ, // FLASH Data bus 8 Bits
88 FL_ADDR, // FLASH Address bus 22 Bits
89 FL_WE_N, // FLASH Write Enable
90 FL_RST_N, // FLASH Reset
91 FL_OE_N, // FLASH Output Enable
92 FL_CE_N, // FLASH Chip Enable
93 ////////////////// // SRAM Interface /////////////// /
94 SRAM_DQ, // SRAM Data bus 16 Bits
95 SRAM_ADDR, // SRAM Address bus 18 Bits
96 SRAM_UB_N, // SRAM High-byte Data Mask
97 SRAM_LB_N, // SRAM Low-byte Data Mask
98 SRAM_WE_N, // SRAM Write Enable
99 SRAM_CE_N, // SRAM Chip Enable
100 SRAM_OE_N, // SRAM Output Enable
101 ////////////////// // ISP1362 Interface /////////////// /
102 OTG_DATA, // ISP1362 Data bus 16 Bits
103 OTG_ADDR, // ISP1362 Address 2 Bits
104 OTG_CS_N, // ISP1362 Chip Select
105 OTG_RD_N, // ISP1362 Write
106 OTG_WR_N, // ISP1362 Read
107 OTG_RST_N, // ISP1362 Reset
108 OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
109 OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
110 OTG_INT0, // ISP1362 Interrupt 0
111 OTG_INT1, // ISP1362 Interrupt 1
112 OTG_DREQ0, // ISP1362 DMA Request 0
113 OTG_DREQ1, // ISP1362 DMA Request 1
114 OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
115 OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
116 ////////////////// // LCD Module 16X2 /////////////// /
117 LCD_ON, // LCD Power ON/OFF
118 LCD_BLON, // LCD Back Light ON/OFF
119 LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
120 LCD_EN, // LCD Enable
121 LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
122 LCD_DATA, // LCD Data bus 8 bits
123 ////////////////// // SD_Card Interface /////////////// /
124 SD_DAT, // SD Card Data
125 SD_DAT3, // SD Card Data 3
126 SD_CMD, // SD Card Command Signal
127 SD_CLK, // SD Card Clock
128 ////////////////// // USB JTAG link ////////////////// //
129 TDI, // CPLD -> FPGA (data in)
130 TCK, // CPLD -> FPGA (clk)
131 TCS, // CPLD -> FPGA (CS)
132 TDO, // FPGA -> CPLD (data out)
133 ////////////////// // I2C /////////////////////////// /
134 I2C_SDAT, // I2C Data
135 I2C_SCLK, // I2C Clock
136 ////////////////// // PS2 /////////////////////////// /
137 PS2_DAT, // PS2 Data
138 PS2_CLK, // PS2 Clock
139 ////////////////// // VGA /////////////////////////// /
140 VGA_CLK, // VGA Clock
141 VGA_HS, // VGA H_SYNC
142 VGA_VS, // VGA V_SYNC
143 VGA_BLANK, // VGA BLANK
144 VGA_SYNC, // VGA SYNC
145 VGA_R, // VGA Red[9:0]
146 VGA_G, // VGA Green[9:0]
147 VGA_B, // VGA Blue[9:0]
148 //////////// Ethernet Interface ////////////////////////
149 ENET_DATA, // DM9000A DATA bus 16Bits
150 ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
151 ENET_CS_N, // DM9000A Chip Select
152 ENET_WR_N, // DM9000A Write
153 ENET_RD_N, // DM9000A Read
154 ENET_RST_N, // DM9000A Reset
155 ENET_INT, // DM9000A Interrupt
156 ENET_CLK, // DM9000A Clock 25 MHz
157 /////////////// / Audio CODEC ////////////////////////
158 AUD_ADCLRCK, // Audio CODEC ADC LR Clock
159 AUD_ADCDAT, // Audio CODEC ADC Data
160 AUD_DACLRCK, // Audio CODEC DAC LR Clock
161 AUD_DACDAT, // Audio CODEC DAC Data
162 AUD_BCLK, // Audio CODEC Bit-Stream Clock
163 AUD_XCK, // Audio CODEC Chip Clock
164 /////////////// / TV Decoder ////////////////////////
165 TD_DATA, // TV Decoder Data bus 8 bits
166 TD_HS, // TV Decoder H_SYNC
167 TD_VS, // TV Decoder V_SYNC
168 TD_RESET, // TV Decoder Reset
169 ////////////////// // GPIO /////////////////////////// /
170 GPIO_0, // GPIO Connection 0
171 GPIO_1 // GPIO Connection 1
172 );
173
174 //////////////////////// Clock Input ////////////////////////
175 input CLOCK_27; // 27 MHz
176 input CLOCK_50; // 50 MHz
177 input EXT_CLOCK; // External Clock
178 //////////////////////// Push Button ////////////////////////
179 input [ 3 : 0 ] KEY; // Pushbutton[3:0]
180 //////////////////////// DPDT Switch ////////////////////////
181 input [ 17 : 0 ] SW; // Toggle Switch[17:0]
182 //////////////////////// 7-SEG Dispaly ////////////////////////
183 output [ 6 : 0 ] HEX0; // Seven Segment Digit 0
184 output [ 6 : 0 ] HEX1; // Seven Segment Digit 1
185 output [ 6 : 0 ] HEX2; // Seven Segment Digit 2
186 output [ 6 : 0 ] HEX3; // Seven Segment Digit 3
187 output [ 6 : 0 ] HEX4; // Seven Segment Digit 4
188 output [ 6 : 0 ] HEX5; // Seven Segment Digit 5
189 output [ 6 : 0 ] HEX6; // Seven Segment Digit 6
190 output [ 6 : 0 ] HEX7; // Seven Segment Digit 7
191 /////////////////////////// / LED /////////////////////////// /
192 output [ 8 : 0 ] LEDG; // LED Green[8:0]
193 output [ 17 : 0 ] LEDR; // LED Red[17:0]
194 /////////////////////////// / UART /////////////////////////// /
195 output UART_TXD; // UART Transmitter
196 input UART_RXD; // UART Receiver
197 /////////////////////////// / IRDA /////////////////////////// /
198 output IRDA_TXD; // IRDA Transmitter
199 input IRDA_RXD; // IRDA Receiver
200 ///////////////////// // SDRAM Interface ////////////////////////
201 inout [ 15 : 0 ] DRAM_DQ; // SDRAM Data bus 16 Bits
202 output [ 11 : 0 ] DRAM_ADDR; // SDRAM Address bus 12 Bits
203 output DRAM_LDQM; // SDRAM Low-byte Data Mask
204 output DRAM_UDQM; // SDRAM High-byte Data Mask
205 output DRAM_WE_N; // SDRAM Write Enable
206 output DRAM_CAS_N; // SDRAM Column Address Strobe
207 output DRAM_RAS_N; // SDRAM Row Address Strobe
208 output DRAM_CS_N; // SDRAM Chip Select
209 output DRAM_BA_0; // SDRAM Bank Address 0
210 output DRAM_BA_1; // SDRAM Bank Address 0
211 output DRAM_CLK; // SDRAM Clock
212 output DRAM_CKE; // SDRAM Clock Enable
213 //////////////////////// Flash Interface ////////////////////////
214 inout [ 7 : 0 ] FL_DQ; // FLASH Data bus 8 Bits
215 output [ 21 : 0 ] FL_ADDR; // FLASH Address bus 22 Bits
216 output FL_WE_N; // FLASH Write Enable
217 output FL_RST_N; // FLASH Reset
218 output FL_OE_N; // FLASH Output Enable
219 output FL_CE_N; // FLASH Chip Enable
220 //////////////////////// SRAM Interface ////////////////////////
221 inout [ 15 : 0 ] SRAM_DQ; // SRAM Data bus 16 Bits
222 output [ 17 : 0 ] SRAM_ADDR; // SRAM Address bus 18 Bits
223 output SRAM_UB_N; // SRAM High-byte Data Mask
224 output SRAM_LB_N; // SRAM Low-byte Data Mask
225 output SRAM_WE_N; // SRAM Write Enable
226 output SRAM_CE_N; // SRAM Chip Enable
227 output SRAM_OE_N; // SRAM Output Enable
228 ////////////////// // ISP1362 Interface ////////////////////////
229 inout [ 15 : 0 ] OTG_DATA; // ISP1362 Data bus 16 Bits
230 output [ 1 : 0 ] OTG_ADDR; // ISP1362 Address 2 Bits
231 output OTG_CS_N; // ISP1362 Chip Select
232 output OTG_RD_N; // ISP1362 Write
233 output OTG_WR_N; // ISP1362 Read
234 output OTG_RST_N; // ISP1362 Reset
235 output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
236 output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
237 input OTG_INT0; // ISP1362 Interrupt 0
238 input OTG_INT1; // ISP1362 Interrupt 1
239 input OTG_DREQ0; // ISP1362 DMA Request 0
240 input OTG_DREQ1; // ISP1362 DMA Request 1
241 output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
242 output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
243 ////////////////// // LCD Module 16X2 /////////////////////////// /
244 inout [ 7 : 0 ] LCD_DATA; // LCD Data bus 8 bits
245 output LCD_ON; // LCD Power ON/OFF
246 output LCD_BLON; // LCD Back Light ON/OFF
247 output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
248 output LCD_EN; // LCD Enable
249 output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
250 ////////////////// // SD Card Interface ////////////////////////
251 inout SD_DAT; // SD Card Data
252 inout SD_DAT3; // SD Card Data 3
253 inout SD_CMD; // SD Card Command Signal
254 output SD_CLK; // SD Card Clock
255 //////////////////////// I2C ////////////////////////////// //
256 inout I2C_SDAT; // I2C Data
257 output I2C_SCLK; // I2C Clock
258 //////////////////////// PS2 ////////////////////////////// //
259 input PS2_DAT; // PS2 Data
260 input PS2_CLK; // PS2 Clock
261 ////////////////// // USB JTAG link /////////////////////////// /
262 input TDI; // CPLD -> FPGA (data in)
263 input TCK; // CPLD -> FPGA (clk)
264 input TCS; // CPLD -> FPGA (CS)
265 output TDO; // FPGA -> CPLD (data out)
266 //////////////////////// VGA /////////////////////////// /
267 output VGA_CLK; // VGA Clock
268 output VGA_HS; // VGA H_SYNC
269 output VGA_VS; // VGA V_SYNC
270 output VGA_BLANK; // VGA BLANK
271 output VGA_SYNC; // VGA SYNC
272 output [ 9 : 0 ] VGA_R; // VGA Red[9:0]
273 output [ 9 : 0 ] VGA_G; // VGA Green[9:0]
274 output [ 9 : 0 ] VGA_B; // VGA Blue[9:0]
275 /////////////// / Ethernet Interface /////////////////////////// /
276 inout [ 15 : 0 ] ENET_DATA; // DM9000A DATA bus 16Bits
277 output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
278 output ENET_CS_N; // DM9000A Chip Select
279 output ENET_WR_N; // DM9000A Write
280 output ENET_RD_N; // DM9000A Read
281 output ENET_RST_N; // DM9000A Reset
282 input ENET_INT; // DM9000A Interrupt
283 output ENET_CLK; // DM9000A Clock 25 MHz
284 ////////////////// // Audio CODEC /////////////////////////// /
285 inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
286 input AUD_ADCDAT; // Audio CODEC ADC Data
287 inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
288 output AUD_DACDAT; // Audio CODEC DAC Data
289 inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
290 output AUD_XCK; // Audio CODEC Chip Clock
291 ////////////////// // TV Devoder /////////////////////////// /
292 input [ 7 : 0 ] TD_DATA; // TV Decoder Data bus 8 bits
293 input TD_HS; // TV Decoder H_SYNC
294 input TD_VS; // TV Decoder V_SYNC
295 output TD_RESET; // TV Decoder Reset
296 //////////////////////// GPIO ////////////////////////////// //
297 inout [ 35 : 0 ] GPIO_0; // GPIO Connection 0
298 inout [ 35 : 0 ] GPIO_1; // GPIO Connection 1
299
300 assign LCD_ON = 1 ' b1;
301 assign LCD_BLON = 1 ' b1;
302 assign TD_RESET = 1 ' b1;
303
304 // All inout port turn to tri-state
305 assign FL_DQ = 8 ' hzz;
306 assign SRAM_DQ = 16 ' hzzzz;
307 assign OTG_DATA = 16 ' hzzzz;
308 assign LCD_DATA = 8 ' hzz;
309 assign SD_DAT = 1 ' bz;
310 assign I2C_SDAT = 1 ' bz;
311 assign ENET_DATA = 16 ' hzzzz;
312 assign AUD_ADCLRCK = 1 ' bz;
313 assign AUD_DACLRCK = 1 ' bz;
314 assign AUD_BCLK = 1 ' bz;
315
316 // CCD
317 wire [ 9 : 0 ] CCD_DATA;
318 wire CCD_SDAT;
319 wire CCD_SCLK;
320 wire CCD_FLASH;
321 wire CCD_FVAL;
322 wire CCD_LVAL;
323 wire CCD_PIXCLK;
324 reg CCD_MCLK; // CCD Master Clock
325
326 wire [ 15 : 0 ] Read_DATA1;
327 wire [ 15 : 0 ] Read_DATA2;
328 wire VGA_CTRL_CLK;
329 wire AUD_CTRL_CLK;
330 wire [ 9 : 0 ] mCCD_DATA;
331 wire mCCD_DVAL;
332 wire mCCD_DVAL_d;
333 wire [ 10 : 0 ] X_Cont;
334 wire [ 10 : 0 ] Y_Cont;
335 wire [ 9 : 0 ] X_ADDR;
336 wire [ 31 : 0 ] Frame_Cont;
337 wire [ 9 : 0 ] mCCD_R;
338 wire [ 9 : 0 ] mCCD_G;
339 wire [ 9 : 0 ] mCCD_B;
340 wire DLY_RST_0;
341 wire DLY_RST_1;
342 wire DLY_RST_2;
343 wire Read;
344 reg [ 9 : 0 ] rCCD_DATA;
345 reg rCCD_LVAL;
346 reg rCCD_FVAL;
347 wire [ 9 : 0 ] sCCD_R;
348 wire [ 9 : 0 ] sCCD_G;
349 wire [ 9 : 0 ] sCCD_B;
350 wire sCCD_DVAL;
351
352 // RGB2Gray output, VGA_Controller input
353 // add by oomusou 07/14/2008
354 wire [ 9 : 0 ] w_r;
355 wire [ 9 : 0 ] w_g;
356 wire [ 9 : 0 ] w_b;
357
358 // For Sensor 1
359 assign CCD_DATA[ 0 ] = GPIO_1[ 0 ];
360 assign CCD_DATA[ 1 ] = GPIO_1[ 1 ];
361 assign CCD_DATA[ 2 ] = GPIO_1[ 5 ];
362 assign CCD_DATA[ 3 ] = GPIO_1[ 3 ];
363 assign CCD_DATA[ 4 ] = GPIO_1[ 2 ];
364 assign CCD_DATA[ 5 ] = GPIO_1[ 4 ];
365 assign CCD_DATA[ 6 ] = GPIO_1[ 6 ];
366 assign CCD_DATA[ 7 ] = GPIO_1[ 7 ];
367 assign CCD_DATA[ 8 ] = GPIO_1[ 8 ];
368 assign CCD_DATA[ 9 ] = GPIO_1[ 9 ];
369 assign GPIO_1[ 11 ] = CCD_MCLK;
370 // assign GPIO_1[15] = CCD_SDAT;
371 // assign GPIO_1[14] = CCD_SCLK;
372 assign CCD_FVAL = GPIO_1[ 13 ];
373 assign CCD_LVAL = GPIO_1[ 12 ];
374 assign CCD_PIXCLK = GPIO_1[ 10 ];
375 // For Sensor 2
376 /*
377 assign CCD_DATA[0] = GPIO_1[0+20];
378 assign CCD_DATA[1] = GPIO_1[1+20];
379 assign CCD_DATA[2] = GPIO_1[5+20];
380 assign CCD_DATA[3] = GPIO_1[3+20];
381 assign CCD_DATA[4] = GPIO_1[2+20];
382 assign CCD_DATA[5] = GPIO_1[4+20];
383 assign CCD_DATA[6] = GPIO_1[6+20];
384 assign CCD_DATA[7] = GPIO_1[7+20];
385 assign CCD_DATA[8] = GPIO_1[8+20];
386 assign CCD_DATA[9] = GPIO_1[9+20];
387 assign GPIO_1[11+20] = CCD_MCLK;
388 assign GPIO_1[15+20] = CCD_SDAT;
389 assign GPIO_1[14+20] = CCD_SCLK;
390 assign CCD_FVAL = GPIO_1[13+20];
391 assign CCD_LVAL = GPIO_1[12+20];
392 assign CCD_PIXCLK = GPIO_1[10+20];
393 */
394 assign LEDR = SW;
395 assign LEDG = Y_Cont;
396 assign VGA_CTRL_CLK = CCD_MCLK;
397 assign VGA_CLK = ~ CCD_MCLK;
398
399 always@(posedge CLOCK_50) CCD_MCLK <= ~ CCD_MCLK;
400
401 always@(posedge CCD_PIXCLK)
402 begin
403 rCCD_DATA <= CCD_DATA;
404 rCCD_LVAL <= CCD_LVAL;
405 rCCD_FVAL <= CCD_FVAL;
406 end
407
408 VGA_Controller u1 ( // Host Side
409 .oRequest(Read),
410 .iRed(w_r),
411 .iGreen(w_g),
412 .iBlue(w_b),
413 // VGA Side
414 .oVGA_R(VGA_R),
415 .oVGA_G(VGA_G),
416 .oVGA_B(VGA_B),
417 .oVGA_H_SYNC(VGA_HS),
418 .oVGA_V_SYNC(VGA_VS),
419 .oVGA_SYNC(VGA_SYNC),
420 .oVGA_BLANK(VGA_BLANK),
421 // Control Signal
422 .iCLK(VGA_CTRL_CLK),
423 .iRST_N(DLY_RST_2)
424 );
425
426 Reset_Delay u2 (
427 .iCLK(CLOCK_50),
428 .iRST(KEY[ 0 ]),
429 .oRST_0(DLY_RST_0),
430 .oRST_1(DLY_RST_1),
431 .oRST_2(DLY_RST_2)
432 );
433
434 CCD_Capture u3 (
435 .oDATA(mCCD_DATA),
436 .oDVAL(mCCD_DVAL),
437 .oX_Cont(X_Cont),
438 .oY_Cont(Y_Cont),
439 .oFrame_Cont(Frame_Cont),
440 .iDATA(rCCD_DATA),
441 .iFVAL(rCCD_FVAL),
442 .iLVAL(rCCD_LVAL),
443 .iSTART( ! KEY[ 3 ]),
444 .iEND( ! KEY[ 2 ]),
445 .iCLK(CCD_PIXCLK),
446 .iRST(DLY_RST_1)
447 );
448
449 RAW2RGB u4 (
450 .oRed(mCCD_R),
451 .oGreen(mCCD_G),
452 .oBlue(mCCD_B),
453 .oDVAL(mCCD_DVAL_d),
454 .iX_Cont(X_Cont),
455 .iY_Cont(Y_Cont),
456 .iDATA(mCCD_DATA),
457 .iDVAL(mCCD_DVAL),
458 .iCLK(CCD_PIXCLK),
459 .iRST(DLY_RST_1)
460 );
461
462 SEG7_LUT_8 u5 (
463 .oSEG0(HEX0),
464 .oSEG1(HEX1),
465 .oSEG2(HEX2),
466 .oSEG3(HEX3),
467 .oSEG4(HEX4),
468 .oSEG5(HEX5),
469 .oSEG6(HEX6),
470 .oSEG7(HEX7),
471 .iDIG(Frame_Cont)
472 );
473
474 Sdram_Control_4Port u6 ( // HOST Side
475 .REF_CLK(CLOCK_50),
476 .RESET_N( 1 ' b1),
477 // FIFO Write Side 1
478 .WR1_DATA({sCCD_G[ 9 : 5 ], sCCD_B[ 9 : 0 ]}),
479 .WR1(sCCD_DVAL),
480 .WR1_ADDR( 0 ),
481 .WR1_MAX_ADDR( 640 * 512 ),
482 .WR1_LENGTH( 9 ' h100),
483 .WR1_LOAD( ! DLY_RST_0),
484 .WR1_CLK(CCD_PIXCLK),
485 // FIFO Write Side 2
486 .WR2_DATA({sCCD_G[ 4 : 0 ], sCCD_R[ 9 : 0 ]}),
487 .WR2(sCCD_DVAL),
488 .WR2_ADDR( 22 ' h100000),
489 .WR2_MAX_ADDR( 22 ' h100000+640*512),
490 .WR2_LENGTH( 9 ' h100),
491 .WR2_LOAD( ! DLY_RST_0),
492 .WR2_CLK(CCD_PIXCLK),
493 // FIFO Read Side 1
494 .RD1_DATA(Read_DATA1),
495 .RD1(Read),
496 .RD1_ADDR( 640 * 16 ),
497 .RD1_MAX_ADDR( 640 * 496 ),
498 .RD1_LENGTH( 9 ' h100),
499 .RD1_LOAD( ! DLY_RST_0),
500 .RD1_CLK(VGA_CTRL_CLK),
501 // FIFO Read Side 2
502 .RD2_DATA(Read_DATA2),
503 .RD2(Read),
504 .RD2_ADDR( 22 ' h100000+640*16),
505 .RD2_MAX_ADDR( 22 ' h100000+640*496),
506 .RD2_LENGTH( 9 ' h100),
507 .RD2_LOAD( ! DLY_RST_0),
508 .RD2_CLK(VGA_CTRL_CLK),
509 // SDRAM Side
510 .SA(DRAM_ADDR),
511 .BA({DRAM_BA_1,DRAM_BA_0}), .CS_N(DRAM_CS_N),
512 .CKE(DRAM_CKE),
513 .RAS_N(DRAM_RAS_N),
514 .CAS_N(DRAM_CAS_N),
515 .WE_N(DRAM_WE_N),
516 .DQ(DRAM_DQ),
517 .DQM({DRAM_UDQM,DRAM_LDQM}),
518 .SDR_CLK(DRAM_CLK)
519 );
520
521 I2C_CCD_Config u7 ( // Host Side
522 .iCLK(CLOCK_50),
523 .iRST_N(KEY[ 1 ]),
524 .iExposure(SW[ 15 : 0 ]),
525 // I2C Side
526 .I2C_SCLK(GPIO_1[ 14 ]),
527 .I2C_SDAT(GPIO_1[ 15 ])
528 );
529
530 Mirror_Col u8 ( // Input Side
531 .iCCD_R(mCCD_R),
532 .iCCD_G(mCCD_G),
533 .iCCD_B(mCCD_B),
534 .iCCD_DVAL(mCCD_DVAL_d),
535 .iCCD_PIXCLK(CCD_PIXCLK),
536 .iRST_N(DLY_RST_1),
537 // Output Side
538 .oCCD_R(sCCD_R),
539 .oCCD_G(sCCD_G),
540 .oCCD_B(sCCD_B),
541 .oCCD_DVAL(sCCD_DVAL)
542 );
543
544 RGB2Gray u9 (
545 .clk(VGA_CTRL_CLK),
546 .rst_n(DLY_RST_2),
547 .i_r(Read_DATA2[ 9 : 0 ]),
548 .i_g({Read_DATA1[ 14 : 10 ],Read_DATA2[ 14 : 10 ]}),
549 .i_b(Read_DATA1[ 9 : 0 ]),
550 .o_r(w_r),
551 .o_g(w_g),
552 .o_b(w_b)
553 );
554
555 endmodule
2 // Copyright (c) 2005 by Terasic Technologies Inc.
3 // --------------------------------------------------------------------
4 //
5 // Permission:
6 //
7 // Terasic grants permission to use and modify this code for use
8 // in synthesis for all Terasic Development Boards and Altera Development
9 // Kits made by Terasic. Other use of this code, including the selling
10 // ,duplication, or modification of any portion is strictly prohibited.
11 //
12 // Disclaimer:
13 //
14 // This VHDL/Verilog or C/C++ source code is intended as a design reference
15 // which illustrates how these types of functions can be implemented.
16 // It is the user's responsibility to verify their design for
17 // consistency and functionality through the use of formal
18 // verification methods. Terasic provides no warranty regarding the use
19 // or functionality of this code.
20 //
21 // --------------------------------------------------------------------
22 //
23 // Terasic Technologies Inc
24 // 356 Fu-Shin E. Rd Sec. 1. JhuBei City,
25 // HsinChu County, Taiwan
26 // 302
27 //
28 // web: http://www.terasic.com/
29 // email: [email protected]
30 //
31 // --------------------------------------------------------------------
32 //
33 // Major Functions: DE2 CMOS Camera Demo
34 //
35 // --------------------------------------------------------------------
36 //
37 // Revision History :
38 // --------------------------------------------------------------------
39 // Ver :| Author :| Mod. Date :| Changes Made:
40 // V1.0 :| Johnny Chen :| 06/01/06 :| Initial Revision
41 // V1.1 :| Johnny Chen :| 06/02/06 :| Modify Image Quality
42 // V1.2 :| Johnny Chen :| 06/03/22 :| Change Pin Assignment For New Sensor
43 // V1.3 :| Johnny Chen :| 06/03/22 :| Fixed to Compatible with Quartus II 6.0
44 // --------------------------------------------------------------------
45
46 module DE2_CCD (
47 ////////////////// // Clock Input ////////////////// //
48 CLOCK_27, // 27 MHz
49 CLOCK_50, // 50 MHz
50 EXT_CLOCK, // External Clock
51 ////////////////// // Push Button ////////////////// //
52 KEY, // Pushbutton[3:0]
53 ////////////////// // DPDT Switch ////////////////// //
54 SW, // Toggle Switch[17:0]
55 ////////////////// // 7-SEG Dispaly ////////////////// //
56 HEX0, // Seven Segment Digit 0
57 HEX1, // Seven Segment Digit 1
58 HEX2, // Seven Segment Digit 2
59 HEX3, // Seven Segment Digit 3
60 HEX4, // Seven Segment Digit 4
61 HEX5, // Seven Segment Digit 5
62 HEX6, // Seven Segment Digit 6
63 HEX7, // Seven Segment Digit 7
64 //////////////////////// LED ////////////////////////
65 LEDG, // LED Green[8:0]
66 LEDR, // LED Red[17:0]
67 //////////////////////// UART ////////////////////////
68 UART_TXD, // UART Transmitter
69 UART_RXD, // UART Receiver
70 //////////////////////// IRDA ////////////////////////
71 IRDA_TXD, // IRDA Transmitter
72 IRDA_RXD, // IRDA Receiver
73 ///////////////////// SDRAM Interface /////////////// /
74 DRAM_DQ, // SDRAM Data bus 16 Bits
75 DRAM_ADDR, // SDRAM Address bus 12 Bits
76 DRAM_LDQM, // SDRAM Low-byte Data Mask
77 DRAM_UDQM, // SDRAM High-byte Data Mask
78 DRAM_WE_N, // SDRAM Write Enable
79 DRAM_CAS_N, // SDRAM Column Address Strobe
80 DRAM_RAS_N, // SDRAM Row Address Strobe
81 DRAM_CS_N, // SDRAM Chip Select
82 DRAM_BA_0, // SDRAM Bank Address 0
83 DRAM_BA_1, // SDRAM Bank Address 0
84 DRAM_CLK, // SDRAM Clock
85 DRAM_CKE, // SDRAM Clock Enable
86 ////////////////// // Flash Interface /////////////// /
87 FL_DQ, // FLASH Data bus 8 Bits
88 FL_ADDR, // FLASH Address bus 22 Bits
89 FL_WE_N, // FLASH Write Enable
90 FL_RST_N, // FLASH Reset
91 FL_OE_N, // FLASH Output Enable
92 FL_CE_N, // FLASH Chip Enable
93 ////////////////// // SRAM Interface /////////////// /
94 SRAM_DQ, // SRAM Data bus 16 Bits
95 SRAM_ADDR, // SRAM Address bus 18 Bits
96 SRAM_UB_N, // SRAM High-byte Data Mask
97 SRAM_LB_N, // SRAM Low-byte Data Mask
98 SRAM_WE_N, // SRAM Write Enable
99 SRAM_CE_N, // SRAM Chip Enable
100 SRAM_OE_N, // SRAM Output Enable
101 ////////////////// // ISP1362 Interface /////////////// /
102 OTG_DATA, // ISP1362 Data bus 16 Bits
103 OTG_ADDR, // ISP1362 Address 2 Bits
104 OTG_CS_N, // ISP1362 Chip Select
105 OTG_RD_N, // ISP1362 Write
106 OTG_WR_N, // ISP1362 Read
107 OTG_RST_N, // ISP1362 Reset
108 OTG_FSPEED, // USB Full Speed, 0 = Enable, Z = Disable
109 OTG_LSPEED, // USB Low Speed, 0 = Enable, Z = Disable
110 OTG_INT0, // ISP1362 Interrupt 0
111 OTG_INT1, // ISP1362 Interrupt 1
112 OTG_DREQ0, // ISP1362 DMA Request 0
113 OTG_DREQ1, // ISP1362 DMA Request 1
114 OTG_DACK0_N, // ISP1362 DMA Acknowledge 0
115 OTG_DACK1_N, // ISP1362 DMA Acknowledge 1
116 ////////////////// // LCD Module 16X2 /////////////// /
117 LCD_ON, // LCD Power ON/OFF
118 LCD_BLON, // LCD Back Light ON/OFF
119 LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
120 LCD_EN, // LCD Enable
121 LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
122 LCD_DATA, // LCD Data bus 8 bits
123 ////////////////// // SD_Card Interface /////////////// /
124 SD_DAT, // SD Card Data
125 SD_DAT3, // SD Card Data 3
126 SD_CMD, // SD Card Command Signal
127 SD_CLK, // SD Card Clock
128 ////////////////// // USB JTAG link ////////////////// //
129 TDI, // CPLD -> FPGA (data in)
130 TCK, // CPLD -> FPGA (clk)
131 TCS, // CPLD -> FPGA (CS)
132 TDO, // FPGA -> CPLD (data out)
133 ////////////////// // I2C /////////////////////////// /
134 I2C_SDAT, // I2C Data
135 I2C_SCLK, // I2C Clock
136 ////////////////// // PS2 /////////////////////////// /
137 PS2_DAT, // PS2 Data
138 PS2_CLK, // PS2 Clock
139 ////////////////// // VGA /////////////////////////// /
140 VGA_CLK, // VGA Clock
141 VGA_HS, // VGA H_SYNC
142 VGA_VS, // VGA V_SYNC
143 VGA_BLANK, // VGA BLANK
144 VGA_SYNC, // VGA SYNC
145 VGA_R, // VGA Red[9:0]
146 VGA_G, // VGA Green[9:0]
147 VGA_B, // VGA Blue[9:0]
148 //////////// Ethernet Interface ////////////////////////
149 ENET_DATA, // DM9000A DATA bus 16Bits
150 ENET_CMD, // DM9000A Command/Data Select, 0 = Command, 1 = Data
151 ENET_CS_N, // DM9000A Chip Select
152 ENET_WR_N, // DM9000A Write
153 ENET_RD_N, // DM9000A Read
154 ENET_RST_N, // DM9000A Reset
155 ENET_INT, // DM9000A Interrupt
156 ENET_CLK, // DM9000A Clock 25 MHz
157 /////////////// / Audio CODEC ////////////////////////
158 AUD_ADCLRCK, // Audio CODEC ADC LR Clock
159 AUD_ADCDAT, // Audio CODEC ADC Data
160 AUD_DACLRCK, // Audio CODEC DAC LR Clock
161 AUD_DACDAT, // Audio CODEC DAC Data
162 AUD_BCLK, // Audio CODEC Bit-Stream Clock
163 AUD_XCK, // Audio CODEC Chip Clock
164 /////////////// / TV Decoder ////////////////////////
165 TD_DATA, // TV Decoder Data bus 8 bits
166 TD_HS, // TV Decoder H_SYNC
167 TD_VS, // TV Decoder V_SYNC
168 TD_RESET, // TV Decoder Reset
169 ////////////////// // GPIO /////////////////////////// /
170 GPIO_0, // GPIO Connection 0
171 GPIO_1 // GPIO Connection 1
172 );
173
174 //////////////////////// Clock Input ////////////////////////
175 input CLOCK_27; // 27 MHz
176 input CLOCK_50; // 50 MHz
177 input EXT_CLOCK; // External Clock
178 //////////////////////// Push Button ////////////////////////
179 input [ 3 : 0 ] KEY; // Pushbutton[3:0]
180 //////////////////////// DPDT Switch ////////////////////////
181 input [ 17 : 0 ] SW; // Toggle Switch[17:0]
182 //////////////////////// 7-SEG Dispaly ////////////////////////
183 output [ 6 : 0 ] HEX0; // Seven Segment Digit 0
184 output [ 6 : 0 ] HEX1; // Seven Segment Digit 1
185 output [ 6 : 0 ] HEX2; // Seven Segment Digit 2
186 output [ 6 : 0 ] HEX3; // Seven Segment Digit 3
187 output [ 6 : 0 ] HEX4; // Seven Segment Digit 4
188 output [ 6 : 0 ] HEX5; // Seven Segment Digit 5
189 output [ 6 : 0 ] HEX6; // Seven Segment Digit 6
190 output [ 6 : 0 ] HEX7; // Seven Segment Digit 7
191 /////////////////////////// / LED /////////////////////////// /
192 output [ 8 : 0 ] LEDG; // LED Green[8:0]
193 output [ 17 : 0 ] LEDR; // LED Red[17:0]
194 /////////////////////////// / UART /////////////////////////// /
195 output UART_TXD; // UART Transmitter
196 input UART_RXD; // UART Receiver
197 /////////////////////////// / IRDA /////////////////////////// /
198 output IRDA_TXD; // IRDA Transmitter
199 input IRDA_RXD; // IRDA Receiver
200 ///////////////////// // SDRAM Interface ////////////////////////
201 inout [ 15 : 0 ] DRAM_DQ; // SDRAM Data bus 16 Bits
202 output [ 11 : 0 ] DRAM_ADDR; // SDRAM Address bus 12 Bits
203 output DRAM_LDQM; // SDRAM Low-byte Data Mask
204 output DRAM_UDQM; // SDRAM High-byte Data Mask
205 output DRAM_WE_N; // SDRAM Write Enable
206 output DRAM_CAS_N; // SDRAM Column Address Strobe
207 output DRAM_RAS_N; // SDRAM Row Address Strobe
208 output DRAM_CS_N; // SDRAM Chip Select
209 output DRAM_BA_0; // SDRAM Bank Address 0
210 output DRAM_BA_1; // SDRAM Bank Address 0
211 output DRAM_CLK; // SDRAM Clock
212 output DRAM_CKE; // SDRAM Clock Enable
213 //////////////////////// Flash Interface ////////////////////////
214 inout [ 7 : 0 ] FL_DQ; // FLASH Data bus 8 Bits
215 output [ 21 : 0 ] FL_ADDR; // FLASH Address bus 22 Bits
216 output FL_WE_N; // FLASH Write Enable
217 output FL_RST_N; // FLASH Reset
218 output FL_OE_N; // FLASH Output Enable
219 output FL_CE_N; // FLASH Chip Enable
220 //////////////////////// SRAM Interface ////////////////////////
221 inout [ 15 : 0 ] SRAM_DQ; // SRAM Data bus 16 Bits
222 output [ 17 : 0 ] SRAM_ADDR; // SRAM Address bus 18 Bits
223 output SRAM_UB_N; // SRAM High-byte Data Mask
224 output SRAM_LB_N; // SRAM Low-byte Data Mask
225 output SRAM_WE_N; // SRAM Write Enable
226 output SRAM_CE_N; // SRAM Chip Enable
227 output SRAM_OE_N; // SRAM Output Enable
228 ////////////////// // ISP1362 Interface ////////////////////////
229 inout [ 15 : 0 ] OTG_DATA; // ISP1362 Data bus 16 Bits
230 output [ 1 : 0 ] OTG_ADDR; // ISP1362 Address 2 Bits
231 output OTG_CS_N; // ISP1362 Chip Select
232 output OTG_RD_N; // ISP1362 Write
233 output OTG_WR_N; // ISP1362 Read
234 output OTG_RST_N; // ISP1362 Reset
235 output OTG_FSPEED; // USB Full Speed, 0 = Enable, Z = Disable
236 output OTG_LSPEED; // USB Low Speed, 0 = Enable, Z = Disable
237 input OTG_INT0; // ISP1362 Interrupt 0
238 input OTG_INT1; // ISP1362 Interrupt 1
239 input OTG_DREQ0; // ISP1362 DMA Request 0
240 input OTG_DREQ1; // ISP1362 DMA Request 1
241 output OTG_DACK0_N; // ISP1362 DMA Acknowledge 0
242 output OTG_DACK1_N; // ISP1362 DMA Acknowledge 1
243 ////////////////// // LCD Module 16X2 /////////////////////////// /
244 inout [ 7 : 0 ] LCD_DATA; // LCD Data bus 8 bits
245 output LCD_ON; // LCD Power ON/OFF
246 output LCD_BLON; // LCD Back Light ON/OFF
247 output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read
248 output LCD_EN; // LCD Enable
249 output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data
250 ////////////////// // SD Card Interface ////////////////////////
251 inout SD_DAT; // SD Card Data
252 inout SD_DAT3; // SD Card Data 3
253 inout SD_CMD; // SD Card Command Signal
254 output SD_CLK; // SD Card Clock
255 //////////////////////// I2C ////////////////////////////// //
256 inout I2C_SDAT; // I2C Data
257 output I2C_SCLK; // I2C Clock
258 //////////////////////// PS2 ////////////////////////////// //
259 input PS2_DAT; // PS2 Data
260 input PS2_CLK; // PS2 Clock
261 ////////////////// // USB JTAG link /////////////////////////// /
262 input TDI; // CPLD -> FPGA (data in)
263 input TCK; // CPLD -> FPGA (clk)
264 input TCS; // CPLD -> FPGA (CS)
265 output TDO; // FPGA -> CPLD (data out)
266 //////////////////////// VGA /////////////////////////// /
267 output VGA_CLK; // VGA Clock
268 output VGA_HS; // VGA H_SYNC
269 output VGA_VS; // VGA V_SYNC
270 output VGA_BLANK; // VGA BLANK
271 output VGA_SYNC; // VGA SYNC
272 output [ 9 : 0 ] VGA_R; // VGA Red[9:0]
273 output [ 9 : 0 ] VGA_G; // VGA Green[9:0]
274 output [ 9 : 0 ] VGA_B; // VGA Blue[9:0]
275 /////////////// / Ethernet Interface /////////////////////////// /
276 inout [ 15 : 0 ] ENET_DATA; // DM9000A DATA bus 16Bits
277 output ENET_CMD; // DM9000A Command/Data Select, 0 = Command, 1 = Data
278 output ENET_CS_N; // DM9000A Chip Select
279 output ENET_WR_N; // DM9000A Write
280 output ENET_RD_N; // DM9000A Read
281 output ENET_RST_N; // DM9000A Reset
282 input ENET_INT; // DM9000A Interrupt
283 output ENET_CLK; // DM9000A Clock 25 MHz
284 ////////////////// // Audio CODEC /////////////////////////// /
285 inout AUD_ADCLRCK; // Audio CODEC ADC LR Clock
286 input AUD_ADCDAT; // Audio CODEC ADC Data
287 inout AUD_DACLRCK; // Audio CODEC DAC LR Clock
288 output AUD_DACDAT; // Audio CODEC DAC Data
289 inout AUD_BCLK; // Audio CODEC Bit-Stream Clock
290 output AUD_XCK; // Audio CODEC Chip Clock
291 ////////////////// // TV Devoder /////////////////////////// /
292 input [ 7 : 0 ] TD_DATA; // TV Decoder Data bus 8 bits
293 input TD_HS; // TV Decoder H_SYNC
294 input TD_VS; // TV Decoder V_SYNC
295 output TD_RESET; // TV Decoder Reset
296 //////////////////////// GPIO ////////////////////////////// //
297 inout [ 35 : 0 ] GPIO_0; // GPIO Connection 0
298 inout [ 35 : 0 ] GPIO_1; // GPIO Connection 1
299
300 assign LCD_ON = 1 ' b1;
301 assign LCD_BLON = 1 ' b1;
302 assign TD_RESET = 1 ' b1;
303
304 // All inout port turn to tri-state
305 assign FL_DQ = 8 ' hzz;
306 assign SRAM_DQ = 16 ' hzzzz;
307 assign OTG_DATA = 16 ' hzzzz;
308 assign LCD_DATA = 8 ' hzz;
309 assign SD_DAT = 1 ' bz;
310 assign I2C_SDAT = 1 ' bz;
311 assign ENET_DATA = 16 ' hzzzz;
312 assign AUD_ADCLRCK = 1 ' bz;
313 assign AUD_DACLRCK = 1 ' bz;
314 assign AUD_BCLK = 1 ' bz;
315
316 // CCD
317 wire [ 9 : 0 ] CCD_DATA;
318 wire CCD_SDAT;
319 wire CCD_SCLK;
320 wire CCD_FLASH;
321 wire CCD_FVAL;
322 wire CCD_LVAL;
323 wire CCD_PIXCLK;
324 reg CCD_MCLK; // CCD Master Clock
325
326 wire [ 15 : 0 ] Read_DATA1;
327 wire [ 15 : 0 ] Read_DATA2;
328 wire VGA_CTRL_CLK;
329 wire AUD_CTRL_CLK;
330 wire [ 9 : 0 ] mCCD_DATA;
331 wire mCCD_DVAL;
332 wire mCCD_DVAL_d;
333 wire [ 10 : 0 ] X_Cont;
334 wire [ 10 : 0 ] Y_Cont;
335 wire [ 9 : 0 ] X_ADDR;
336 wire [ 31 : 0 ] Frame_Cont;
337 wire [ 9 : 0 ] mCCD_R;
338 wire [ 9 : 0 ] mCCD_G;
339 wire [ 9 : 0 ] mCCD_B;
340 wire DLY_RST_0;
341 wire DLY_RST_1;
342 wire DLY_RST_2;
343 wire Read;
344 reg [ 9 : 0 ] rCCD_DATA;
345 reg rCCD_LVAL;
346 reg rCCD_FVAL;
347 wire [ 9 : 0 ] sCCD_R;
348 wire [ 9 : 0 ] sCCD_G;
349 wire [ 9 : 0 ] sCCD_B;
350 wire sCCD_DVAL;
351
352 // RGB2Gray output, VGA_Controller input
353 // add by oomusou 07/14/2008
354 wire [ 9 : 0 ] w_r;
355 wire [ 9 : 0 ] w_g;
356 wire [ 9 : 0 ] w_b;
357
358 // For Sensor 1
359 assign CCD_DATA[ 0 ] = GPIO_1[ 0 ];
360 assign CCD_DATA[ 1 ] = GPIO_1[ 1 ];
361 assign CCD_DATA[ 2 ] = GPIO_1[ 5 ];
362 assign CCD_DATA[ 3 ] = GPIO_1[ 3 ];
363 assign CCD_DATA[ 4 ] = GPIO_1[ 2 ];
364 assign CCD_DATA[ 5 ] = GPIO_1[ 4 ];
365 assign CCD_DATA[ 6 ] = GPIO_1[ 6 ];
366 assign CCD_DATA[ 7 ] = GPIO_1[ 7 ];
367 assign CCD_DATA[ 8 ] = GPIO_1[ 8 ];
368 assign CCD_DATA[ 9 ] = GPIO_1[ 9 ];
369 assign GPIO_1[ 11 ] = CCD_MCLK;
370 // assign GPIO_1[15] = CCD_SDAT;
371 // assign GPIO_1[14] = CCD_SCLK;
372 assign CCD_FVAL = GPIO_1[ 13 ];
373 assign CCD_LVAL = GPIO_1[ 12 ];
374 assign CCD_PIXCLK = GPIO_1[ 10 ];
375 // For Sensor 2
376 /*
377 assign CCD_DATA[0] = GPIO_1[0+20];
378 assign CCD_DATA[1] = GPIO_1[1+20];
379 assign CCD_DATA[2] = GPIO_1[5+20];
380 assign CCD_DATA[3] = GPIO_1[3+20];
381 assign CCD_DATA[4] = GPIO_1[2+20];
382 assign CCD_DATA[5] = GPIO_1[4+20];
383 assign CCD_DATA[6] = GPIO_1[6+20];
384 assign CCD_DATA[7] = GPIO_1[7+20];
385 assign CCD_DATA[8] = GPIO_1[8+20];
386 assign CCD_DATA[9] = GPIO_1[9+20];
387 assign GPIO_1[11+20] = CCD_MCLK;
388 assign GPIO_1[15+20] = CCD_SDAT;
389 assign GPIO_1[14+20] = CCD_SCLK;
390 assign CCD_FVAL = GPIO_1[13+20];
391 assign CCD_LVAL = GPIO_1[12+20];
392 assign CCD_PIXCLK = GPIO_1[10+20];
393 */
394 assign LEDR = SW;
395 assign LEDG = Y_Cont;
396 assign VGA_CTRL_CLK = CCD_MCLK;
397 assign VGA_CLK = ~ CCD_MCLK;
398
399 always@(posedge CLOCK_50) CCD_MCLK <= ~ CCD_MCLK;
400
401 always@(posedge CCD_PIXCLK)
402 begin
403 rCCD_DATA <= CCD_DATA;
404 rCCD_LVAL <= CCD_LVAL;
405 rCCD_FVAL <= CCD_FVAL;
406 end
407
408 VGA_Controller u1 ( // Host Side
409 .oRequest(Read),
410 .iRed(w_r),
411 .iGreen(w_g),
412 .iBlue(w_b),
413 // VGA Side
414 .oVGA_R(VGA_R),
415 .oVGA_G(VGA_G),
416 .oVGA_B(VGA_B),
417 .oVGA_H_SYNC(VGA_HS),
418 .oVGA_V_SYNC(VGA_VS),
419 .oVGA_SYNC(VGA_SYNC),
420 .oVGA_BLANK(VGA_BLANK),
421 // Control Signal
422 .iCLK(VGA_CTRL_CLK),
423 .iRST_N(DLY_RST_2)
424 );
425
426 Reset_Delay u2 (
427 .iCLK(CLOCK_50),
428 .iRST(KEY[ 0 ]),
429 .oRST_0(DLY_RST_0),
430 .oRST_1(DLY_RST_1),
431 .oRST_2(DLY_RST_2)
432 );
433
434 CCD_Capture u3 (
435 .oDATA(mCCD_DATA),
436 .oDVAL(mCCD_DVAL),
437 .oX_Cont(X_Cont),
438 .oY_Cont(Y_Cont),
439 .oFrame_Cont(Frame_Cont),
440 .iDATA(rCCD_DATA),
441 .iFVAL(rCCD_FVAL),
442 .iLVAL(rCCD_LVAL),
443 .iSTART( ! KEY[ 3 ]),
444 .iEND( ! KEY[ 2 ]),
445 .iCLK(CCD_PIXCLK),
446 .iRST(DLY_RST_1)
447 );
448
449 RAW2RGB u4 (
450 .oRed(mCCD_R),
451 .oGreen(mCCD_G),
452 .oBlue(mCCD_B),
453 .oDVAL(mCCD_DVAL_d),
454 .iX_Cont(X_Cont),
455 .iY_Cont(Y_Cont),
456 .iDATA(mCCD_DATA),
457 .iDVAL(mCCD_DVAL),
458 .iCLK(CCD_PIXCLK),
459 .iRST(DLY_RST_1)
460 );
461
462 SEG7_LUT_8 u5 (
463 .oSEG0(HEX0),
464 .oSEG1(HEX1),
465 .oSEG2(HEX2),
466 .oSEG3(HEX3),
467 .oSEG4(HEX4),
468 .oSEG5(HEX5),
469 .oSEG6(HEX6),
470 .oSEG7(HEX7),
471 .iDIG(Frame_Cont)
472 );
473
474 Sdram_Control_4Port u6 ( // HOST Side
475 .REF_CLK(CLOCK_50),
476 .RESET_N( 1 ' b1),
477 // FIFO Write Side 1
478 .WR1_DATA({sCCD_G[ 9 : 5 ], sCCD_B[ 9 : 0 ]}),
479 .WR1(sCCD_DVAL),
480 .WR1_ADDR( 0 ),
481 .WR1_MAX_ADDR( 640 * 512 ),
482 .WR1_LENGTH( 9 ' h100),
483 .WR1_LOAD( ! DLY_RST_0),
484 .WR1_CLK(CCD_PIXCLK),
485 // FIFO Write Side 2
486 .WR2_DATA({sCCD_G[ 4 : 0 ], sCCD_R[ 9 : 0 ]}),
487 .WR2(sCCD_DVAL),
488 .WR2_ADDR( 22 ' h100000),
489 .WR2_MAX_ADDR( 22 ' h100000+640*512),
490 .WR2_LENGTH( 9 ' h100),
491 .WR2_LOAD( ! DLY_RST_0),
492 .WR2_CLK(CCD_PIXCLK),
493 // FIFO Read Side 1
494 .RD1_DATA(Read_DATA1),
495 .RD1(Read),
496 .RD1_ADDR( 640 * 16 ),
497 .RD1_MAX_ADDR( 640 * 496 ),
498 .RD1_LENGTH( 9 ' h100),
499 .RD1_LOAD( ! DLY_RST_0),
500 .RD1_CLK(VGA_CTRL_CLK),
501 // FIFO Read Side 2
502 .RD2_DATA(Read_DATA2),
503 .RD2(Read),
504 .RD2_ADDR( 22 ' h100000+640*16),
505 .RD2_MAX_ADDR( 22 ' h100000+640*496),
506 .RD2_LENGTH( 9 ' h100),
507 .RD2_LOAD( ! DLY_RST_0),
508 .RD2_CLK(VGA_CTRL_CLK),
509 // SDRAM Side
510 .SA(DRAM_ADDR),
511 .BA({DRAM_BA_1,DRAM_BA_0}), .CS_N(DRAM_CS_N),
512 .CKE(DRAM_CKE),
513 .RAS_N(DRAM_RAS_N),
514 .CAS_N(DRAM_CAS_N),
515 .WE_N(DRAM_WE_N),
516 .DQ(DRAM_DQ),
517 .DQM({DRAM_UDQM,DRAM_LDQM}),
518 .SDR_CLK(DRAM_CLK)
519 );
520
521 I2C_CCD_Config u7 ( // Host Side
522 .iCLK(CLOCK_50),
523 .iRST_N(KEY[ 1 ]),
524 .iExposure(SW[ 15 : 0 ]),
525 // I2C Side
526 .I2C_SCLK(GPIO_1[ 14 ]),
527 .I2C_SDAT(GPIO_1[ 15 ])
528 );
529
530 Mirror_Col u8 ( // Input Side
531 .iCCD_R(mCCD_R),
532 .iCCD_G(mCCD_G),
533 .iCCD_B(mCCD_B),
534 .iCCD_DVAL(mCCD_DVAL_d),
535 .iCCD_PIXCLK(CCD_PIXCLK),
536 .iRST_N(DLY_RST_1),
537 // Output Side
538 .oCCD_R(sCCD_R),
539 .oCCD_G(sCCD_G),
540 .oCCD_B(sCCD_B),
541 .oCCD_DVAL(sCCD_DVAL)
542 );
543
544 RGB2Gray u9 (
545 .clk(VGA_CTRL_CLK),
546 .rst_n(DLY_RST_2),
547 .i_r(Read_DATA2[ 9 : 0 ]),
548 .i_g({Read_DATA1[ 14 : 10 ],Read_DATA2[ 14 : 10 ]}),
549 .i_b(Read_DATA1[ 9 : 0 ]),
550 .o_r(w_r),
551 .o_g(w_g),
552 .o_b(w_b)
553 );
554
555 endmodule
整個有改的地方如下：
352行
//
RGB2Gray output, VGA_Controller input
// add by oomusou 07/14/2008
wire [ 9 : 0 ] w_r;
wire [ 9 : 0 ] w_g;
wire [ 9 : 0 ] w_b;
// add by oomusou 07/14/2008
wire [ 9 : 0 ] w_r;
wire [ 9 : 0 ] w_g;
wire [ 9 : 0 ] w_b;
宣告了wire供RGB2Gray與VGA_Controller之間的連線
408行
VGA_Controller u1 (
//
Host Side
.oRequest(Read),
.iRed(w_r),
.iGreen(w_g),
.iBlue(w_b),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
// Control Signal
.iCLK(VGA_CTRL_CLK),
.iRST_N(DLY_RST_2)
);
.oRequest(Read),
.iRed(w_r),
.iGreen(w_g),
.iBlue(w_b),
// VGA Side
.oVGA_R(VGA_R),
.oVGA_G(VGA_G),
.oVGA_B(VGA_B),
.oVGA_H_SYNC(VGA_HS),
.oVGA_V_SYNC(VGA_VS),
.oVGA_SYNC(VGA_SYNC),
.oVGA_BLANK(VGA_BLANK),
// Control Signal
.iCLK(VGA_CTRL_CLK),
.iRST_N(DLY_RST_2)
);
VGA_Controller例化上，原來是直接從SDRAM輸入，現在改成剛剛宣告的w_r、w_g、w_b。
544行
RGB2Gray u9 (
.clk(VGA_CTRL_CLK),
.rst_n(DLY_RST_2),
.i_r(Read_DATA2[ 9 : 0 ]),
.i_g({Read_DATA1[ 14 : 10 ],Read_DATA2[ 14 : 10 ]}),
.i_b(Read_DATA1[ 9 : 0 ]),
.o_r(w_r),
.o_g(w_g),
.o_b(w_b)
);
.clk(VGA_CTRL_CLK),
.rst_n(DLY_RST_2),
.i_r(Read_DATA2[ 9 : 0 ]),
.i_g({Read_DATA1[ 14 : 10 ],Read_DATA2[ 14 : 10 ]}),
.i_b(Read_DATA1[ 9 : 0 ]),
.o_r(w_r),
.o_g(w_g),
.o_b(w_b)
);
RGB2Gray的例化，將SDRAM的資料送進RGB2Gray做灰階轉換。
完整程式碼下載
DE2_CCD_gray.7z
Conclusion
整個架構其實相當簡單，唯RGB轉灰階並不是用最嚴謹的演算法，可以就這個地方加以改善，或加上pipeline。
See Also
(原創) 如何控制DE2 VGA輸出時某座標的顏色? (IC Design) (DE2) (Quartus II)
(原創) 如何將CMOS所擷取的影像傳到PC端? (IC Design) (DE2)
(原創) 如何在DE2將CCD影像顯示在彩色LCD上? (純硬體篇) (IC Design) (DE2)
(原創) 如何解決DE2範例DE2_CCD_detect左右相反的問題? (IC Design) (DE2) (Quartus II)
(原創) 如何Real Time產生灰階影像? (SOC) (DE2) (TRDB-DC2)