VHDL编写二位数值比较器

VHDL编写二位数值比较器

二位数值比较器是由四个输入端和三个输出端组成的比较器，实现两个二位二进制数大小的比较（用高低电平来表示输入输出）真值表如下：

（xx表任意状态）
因此设计时，定义4个输入端和3个输出端的实体，分别为A1A0,B1B0和f1(a>b)f2(a 具体代码如下：

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY homework2 IS
	PORT(A1:IN STD_LOGIC;             --定义4个输入端和3个输出端
		 A0:IN STD_LOGIC;
		 B1:IN STD_LOGIC;
		 B0:IN STD_LOGIC;
		 f1:OUT STD_LOGIC;
		 f2:OUT STD_LOGIC;
		 f3:OUT STD_LOGIC);
END homework2;
ARCHITECTURE HA OF homework2 IS
SIGNAL tmp:STD_LOGIC_VECTOR(3 DOWNTO 0);--定义一个信号数组
BEGIN
tmp<=A1 & B1 & A0 & B0;                 --用&连接四个输入值，并赋值给tmp
PROCESS(tmp)
BEGIN
	CASE tmp IS                         --CASE语句实现具体代码
		WHEN "0000" =>f1<='0';f2<='0';f3<='1';
		WHEN "0001" =>f1<='0';f2<='1';f3<='0';
		WHEN "0010" =>f1<='1';f2<='0';f3<='0';
		WHEN "0011" =>f1<='0';f2<='0';f3<='1';
		WHEN "0100" =>f1<='0';f2<='1';f3<='0';
		WHEN "0101" =>f1<='0';f2<='1';f3<='0';
		WHEN "0110" =>f1<='0';f2<='1';f3<='0';
		WHEN "0111" =>f1<='0';f2<='1';f3<='0';
		WHEN "1000" =>f1<='1';f2<='0';f3<='0';
		WHEN "1001" =>f1<='1';f2<='0';f3<='0';
		WHEN "1010" =>f1<='1';f2<='0';f3<='0';
		WHEN "1011" =>f1<='1';f2<='0';f3<='0';
		WHEN "1100" =>f1<='0';f2<='0';f3<='1';
		WHEN "1101" =>f1<='0';f2<='1';f3<='0';
		WHEN "1110" =>f1<='1';f2<='0';f3<='0';
		WHEN "1111" =>f1<='0';f2<='0';f3<='1';
	END CASE;
END PROCESS;
END HA;

仿真结果如下：