VHDL赋值语句

result  <= temp;

上述语句在运行时，可以实时赋值。

architecture Behavioral of top is


    COMPONENT sum
    PORT(
        rst         : IN std_logic;
        clk         : IN std_logic;
        a           : IN std_logic_vector(3 downto 0);
        b           : IN std_logic_vector(3 downto 0);          
        dout        : OUT std_logic_vector(3 downto 0)
        );
    END COMPONENT;

    signal temp     : std_logic_vector(3 downto 0);

begin
    sum_inst: sum PORT MAP(
        rst         => rst, 
        clk         => clk,
        a           => a,
        b           => b,
        dout        => temp 
    );

    result  <= temp;

end Behavioral;

其中sum模块用于计算两路输入信号之和，在时钟上升沿触发计算。仿真结果如下：