基于quartus ii两个4位二进制数相减的VHDL程序（结果在数码管上用十进制显示）

程序未考虑number1 代码：

library ieee;
use ieee.std_logic_1164.all;
Use ieee.std_logic_unsigned.all;
use ieee.STD_LOGIC_ARITH.all;
entity tube is
	port(number1,number2: in std_logic_vector(3 downto 0);
		clk : in std_logic;
		SG : out std_logic_vector(7 downto 0);--段控制信号输出，单个数码管字符显示
		BT : out std_logic_vector(7 downto 0) --位控制信号输出，八个数码管的选择
		);
end tube;
architecture behave of tube is
	signal scan : integer range 0 to 1;
	signal ledag1,ledag2 : std_logic_vector(7 downto 0);--两个数码管的动态显示
    signal cnt_One,cnt_Ten:integer range 0 to 9 :=0;
   	Signal data:integer range 0 to 15;
begin
data<=conv_integer(number1-number2);
process(clk)
  begin 
	if (clk'event and clk='1') then
		cnt_one<=data rem 10;
		cnt_ten<=(data-cnt_one)/10;
		if(scan=1)then
			scan<=0;
		else
			scan<=scan+1;
		end if;	
		end if;	
end process;
--译码电路1，数码管1动态字符查表
process(cnt_One)
	begin
    case cnt_One is
	  when 0=>ledag1<="11111100";
      when 1=>ledag1<="01100000";
      when 2=>ledag1<="11011010";
      when 3=>ledag1<="11110010";
      when 4=>ledag1<="01100110";
      when 5=>ledag1<="10110110";
      when 6=>ledag1<="10111110";
      when 7=>ledag1<="11100000";
      when 8=>ledag1<="11111110";
      when 9=>ledag1<="11110110";
      when others=>Null;
		end case;
end process ;
--译码电路2，数码管2动态字符查表
 process(cnt_Ten)
	begin
    case cnt_Ten is
	  when 0=>ledag2<="11111100";
      when 1=>ledag2<="01100000";
      when 2=>ledag2<="11011010";
      when 3=>ledag2<="11110010";
      when 4=>ledag2<="01100110";
      when 5=>ledag2<="10110110";
      when 6=>ledag2<="10111110";
      when 7=>ledag2<="11100000";
      when 8=>ledag2<="11111110";
      when 9=>ledag2<="11110110";
      when others=>Null;
	end case;
end process ；
--刷新显示模块	
 process(scan)
	begin 
		case scan is
			when 0 => SG <= ledag1;BT <= "11111110";--数码管1
			when 1 => SG <= ledag2;BT <= "11111101";--数码管2
			when others => Null;
		end case;
	end process ;	
end behave;