VHDL实例化过程
第二步：建立一个名为MUX_0的乘法器
第三步：在程序中例化，看以下程序。
-- 该程序用来实现复数的乘法，端口分别定义的复数的
-- 输入的实部和虚部和输出的实部和虚部
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY LPM;
USE LPM.LPM_COMPONENTS.ALL;
ENTITY plural_mux IS
PORT(
r_in : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
i_in : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
r_out : OUT STD_LOGIC_VECTOR( 15 DOWNTO 0 );
i_out : OUT STD_LOGIC_VECTOR( 15 DOWNTO 0 );
clk : IN STD_LOGIC;
rst_n : IN STD_LOGIC
);
END plural_mux;
ARCHITECTURE beh OF plural_mux IS
--乘法器的例化声明
--在这里我们要注意，例化的声明和和信号的定义都是在ARCHITECTURE的BEGIN之前--的
COMPONENT MUX_0
PORT(clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
datab : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
result : OUT STD_LOGIC_VECTOR( 15 DOWNTO 0 )
);
END COMPONENT;
COMPONENT ADD_SUB_0
PORT (
add_sub : IN STD_LOGIC;
clock : IN STD_LOGIC;
dataa : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END COMPONENT;
SIGNAL r_in_reg1 : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL r_in_reg2 : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL i_in_reg1 : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL i_in_reg2 : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL mux_reg1:STD_LOGIC_VECTOR( 15 DOWNTO 0 );
SIGNAL mux_reg2:STD_LOGIC_VECTOR( 15 DOWNTO 0 );
SIGNAL mux_reg3:STD_LOGIC_VECTOR( 15 DOWNTO 0 );
SIGNAL mux_reg4:STD_LOGIC_VECTOR( 15 DOWNTO 0 );
SIGNAL ad_sb_o1 :STD_LOGIC_VECTOR(15 DOWNTO 0 );
SIGNAL ad_sb_o2 :STD_LOGIC_VECTOR(15 DOWNTO 0 );
BEGIN
PROCESS( clk ,rst_n)
BEGIN
IF ( rst_n = '0' )THEN
r_in_reg1 <= "00000000";
r_in_reg2 <= "00000000";
i_in_reg1 <= "00000000";
i_in_reg2 <= "00000000";
ELSIF( clk'EVENT AND clk = '1') THEN
r_in_reg1 <= r_in;
r_in_reg2 <= r_in_reg1;
i_in_reg1 <= i_in;
i_in_reg2 <= i_in_reg1;
END IF;
END PROCESS;
--乘法器的例化实例
I_MUX_00 : MUX_0
PORT MAP (clk,r_in_reg1, r_in_reg2,mux_reg1);
I_MUX_01 : MUX_0
PORT MAP (clk,r_in_reg1, i_in_reg2,mux_reg2);
I_MUX_02 : MUX_0
PORT MAP (clk,i_in_reg1, r_in_reg2,mux_reg3);
I_MUX_04 : MUX_0
PORT MAP (clk,i_in_reg1, i_in_reg2,mux_reg4);
I_ADD_SUB_00 : ADD_SUB_0
PORT MAP('0',clk,mux_reg1,mux_reg4,ad_sb_o1);
I_ADD_SUB_02 : ADD_SUB_0
PORT MAP('1',clk,mux_reg2,mux_reg3,ad_sb_o2);
r_out <= ad_sb_o1;
i_out <= ad_sb_o2;
END beh;