VHDL之Aggregate

Definition

A basic operation that combines one or more values into a composite value of a record or array type.

Example 1

variable Data_1 : BIT_VECTOR (0 to 3) := ('0','1','0','1');

Example 2

variable Data_2 : BIT_VECTOR (0 to 3) := (1=>'1',0=>'0',3=>'1',2=>'0');

　　bits 0 and 2 are assigned  '0', while bits 1 and 3 are assigned '1'. 

Example 3

signal Data_Bus : std_logic_vector (15 downto 0);

... ...

Data_Bus <= (15 downto 8 => '0', 7 downto 0 => '1');

　　Data_Bus will be assigned "0000_0000_1111_1111". 

Example 4

type Status_Record is record

    Code　　: Integer;

    Name　　: String(1 to 4);

end record;

variable Status_var : Status_Record := (Code => 57, Name => "MOVE");

　　each element is associated a value (of the same type as the element itself).

Example 5

signal Data_Bus : std_logic_vector (15 downto 0);

... ...

Data_Bus <= (14 downto 8 => '0', others => '1');

　　bits 14 through 8 receive value '0' and all the others (15 and 7 through 0) will be assigned '1'. 

Example 6

signal Data_Bus : std_logic_vector (15 downto 0);

... ...

Data_Bus <= (others => 'Z');

　　aggregate with the others choice representing all the elements can be used.

Example 7

signal Data_Bus : std_logic_vector (15 downto 0);

... ...

Data_Bus <= (15 | 7 downto 0 => '1', others => '0');

　　Note the multiple choice specification of the assignment to the bits 15 and 7 through 0. The result of the assignment to Data_Bus will be the same as in examples 3 and 5 ("1000_0000_1111_1111").