CSCI 2121

CSCI 2121: Computer Organization and
Assembly Language
Lab 4
Design Sequential Circuits in Verilog II
Thursday 14th February, 2019
1 Learning Objectives
In this lab, you will learn to interpret Verilog for testbenches.
You will learn case statements, serial and parallel data transfer.
You will implement a vending machine.
2 Submission Instruction
Save code for each task as .sv file, with the name specified at the end of each lab task.
Put all lab files into one folder, and compress the folder to a .zip file.
Submit it on Brightspace.
Deadline for submission: Sunday 17th February, 2019, 11:55 pm.
As the marking will be done automatically by a script, it is important that you follow
these instructions and save your files with correct names and .sv extension.
1
3 Lab Assignment
3.1 Lab Task 1: Frequency Divider
A frequency divider takes only a clock as input, which constantly alternates producing 1
and 0, and produces a lower frequency alternating signal. We will make a circuit to quarter the
input rate. Every time the clock pulses four times, we would like to set our output to be the
opposite of the current output. To do this, we will negate our output when the clock’s state
is 0. In order to keep track of four clock pulses, we need two state bits. The skeleton code is
available at https://www.edaplayground.com... Name your file as task1.sv
Hint: you can use either if. . . else, or case, or (ternary operator) to complete the always
block.
3.2 Lab Task 2: Vending Machine
Using previous knowledge of sequential circuits, you will now construct a vending machine
controller according to the following specifications. The circuit has four inputs: clk, quarter,
loonie, and toonie. The controller also has two outputs: change and dispense. Change
is a 3-bit bus which outputs a binary number indicating the number of quarters to dispense.
Dispense is a single on/off wire. You must implement the controller based on the following
properties. The skeleton code is available at https://www.edaplayground.com... Name
your file as task2.sv

1. The item (and change, if any) is dispensed when $1 is inserted into the machine.
2. Change outputs a binary number indicating the number of quarters to dispense.
3. The dispense and change signals are set to 1 on the same clock tick that the amount is
   met.
   Note: In the lecture, you designed sequential circuits using 6 steps from specification to
   minimizing the circuit. In Verilog, however, you need to mainly focus on the specification and
   the state transition diagram. The rest of the circuit design is done with high-level Verilog
   statements.
   WX：codehelp