【方案解决】ncelab: *E,CUIOCP Out-of-module reference terminating in a VHDL scope is not allowed

Error Message	ncelab: *E,CUIOCP Out-of-module reference terminating in a VHDL scope is not allowed
Definition	This solution addresses the following points regarding accessing internal signals between Verilog and VHDL domains :   Q1:The ncelab error CUIOCP as shown above :   Scenario : I have a mixed language design : RTL in VHDL, instantiated in verilog testbench. I need to refer to an internal signal of VHDL code. How can I reference this from my verilog top-level ?   The code snippet below gives elaboration error CUIOCP: *** initial begin var_a = 1'b0; @(posedge top.m10.v1.inst_btm.r_io); var_a = 1'b1 end *** top : Verilog top m10: vhdl instantiation in verilog v1: verilog instantiation in vhdl inst_btm: vhdl instantiation in verilog r_io: vhdl signal   The above code compiles properly but it gives elaboration error CUIOCP.   Q2-1: How to access a signal deep down the hierarchy from the top level when the design is Mixed HDL (Verilog-VHDL-Verilog)   Q2-2: How to access a signal deep down the hierarchy from the top level when the design is Mixed HDL (VHDL-Verilog-VHDL)   Q3:Case sensitivity in the nc_mirror path for Verilog and VHDL
Solution	A1: Resolving the ncelab error CUIOCP :   Mixed language OOMRs (out-of-module reference) have a restriction that they cannot end in a VHDL scope, as can be seen in the extended help for the error code CUIOCP.   :> nchelp ncelab CUIOCP ncelab/CUIOCP = The out-of-module reference specified terminates in a VHDL scope. Access of a VHDL object through out-of-module reference mechanism is not allowed in mixed language hierarchies.   You can work around this OOMR restriction using the $nc_mirror task in the top Verilog testbench as : ***** reg var_a; reg mirror_signal; initial $nc_mirror( "mirror_signal", "top.m10:v1.inst_btm:r_io", "verbose"); initial begin var_a = 1'b0; @(posedge mirror_signal) var_a = 1'b1 ; end ******   Another solution could be to instantiate a dummy Verilog block inside the target VHDL block which either takes in or drives out signals to the higher-level block. This would create a Verilog unit forthe VerilogOOMR's to use as termination object. Here is example code snippet. entity vhdl_bot signal vhdl_bot : std_logic; component verilog_hack port (hack : in std_logic); end component; inst_hack :verilog_hack port map (vhdl_bot) ; module verilog_hack(hack); input hack; endmodule Since the signal vhdl_bot is now connected in Verilog bottom, it can be directly accessed from anywhere. NOTE A1-1: Attached with this solution is an example testcase that shows the usage of nc_mirror.   NOTE A1-2: Please refer to the Verilog Simulation User Guide or VHDL Simulation User guide - Chapter "Applications" for the syntax details of $nc_mirror system task (Verilog) and nc_mirror procedure (VHDL), along with examples of usage.   A2-1: Attached with this solution is a testcase example that illustrates the use of $nc_mirror system task in a mixed-language hierarchy with Verilog as the top-level. Testcase : nc_mirror_top_vlog.tar.gz   A2-2: Attached with this solution is a testcase example that illustrates the use of nc_mirror procedure in a mixed-language hierarchy with VHDL as the top-level. Testcase : nc_mirror_top_vhd.tar.gz   A3: Case sensitivity in the nc_mirror path for Verilog and VHDL :   It is important to note that the path for nc_mirror is case insensitive for VHDL names and is case sensitive for Verilog names.   That is, if the original nc_mirror calls are as follows :   VHDL: nc_mirror(":mirror_signal", ":v1.inst_btm:r_io", "verbose"); --ORIGINAL Verilog: $nc_mirror( "temp","g1:Forloop1[3].instant1.D_in","verbose"); // ORIGINAL   The following would also work as the VHDL names are case insensitive:   VHDL: nc_mirror(":mirror_signal", ":V1.inst_btm:R_io", "verbose"); -- 'v1' and 'r_io' VHDL case insensitive Verilog: $nc_mirror( "temp","g1:fORLoop1[3].instant1.D_in","verbose"); // 'Forloop1' VHDL case-insensitive   However, the following would *not* work as the Verilog names are case sensitive :   VHDL: nc_mirror(":mirror_signal", ":v1.INST_BTM:r_io", "verbose"); -- 'inst_btm' Verilog case sensitive Verilog: $nc_mirror( "temp","G1:Forloop1[3].instant1.D_in","verbose"); // 'g1' Verilog case-sensitive   This is also illustrated in the two testcases attached to this solution.   In order to change values of signals, use nc_force or nc_deposit utilities as described in the Simulation User Guides.   NOTE: It is the convention to use the different hierarchy separators for mixed language, '.' preceding Verilog units and ':' preceding VHDL units. ncsim does not enforce using the different separators however.