Guidelines for clock

　　用两个256x16的基本存储器构成512x16的数据存储器，因为256x16的基本存储器读写时序不太符合MCU的要求，于是改写之。利用下降沿控制输入，作为基本存储器控制时钟，而上升沿控制数据输出寄存器，满足读写时序要求。借鉴学习ASIC中同时有上升沿和下降沿的设计注意事项。

 

Avoid mixed clock edges

　　= Avoid using both positive-edge and negative-edge triggered flip-flops.

1)　If must use both positive-edge and negative-edge triggered flip-flops, then 

　　- model the worst-case duty cycle of the clock accurately in synthesis and timing annalysis　　

　　- document the assumed duty cycle 

2)　If must use a large number of both positive-edge and negtive-edge triggered FFs, separate them into different modules.

 

Bad example - Mixed clock edges

　　

 

Better example - Negative-edge and positive-edge FFs are separated