generate for例化——Verilog语言练习

HDLBits题目Bcdadd4：
You are provided with a BCD (binary-coded decimal) one-digit adder named bcd_fadd that adds two BCD digits and carry-in, and produces a sum and carry-out.
module bcd_fadd {
input [3:0] a,
input [3:0] b,
input cin,
output cout,
output [3:0] sum );
Instantiate 4 copies of bcd_fadd to create a 4-digit BCD ripple-carry adder. Your adder should add two 4-digit BCD numbers (packed into 16-bit vectors) and a carry-in to produce a 4-digit sum and carry out.

module top_module( 
    input [15:0] a, b,
    input cin,
    output cout,
    output [15:0] sum );

    genvar i;
    wire [3:-1] cout_w;
    assign	cout_w[-1]=cin;
    generate
        for(i=0;i<4;i++)
            begin:bcd_fadd4
                bcd_fadd u(a[(i*4+3):(i*4)],b[(i*4+3):(i*4)],cout_w[i-1],cout_w[i],sum[(i*4+3):(i*4)]);
            end
    endgenerate
    assign cout=cout_w[3];
    
endmodule