[中英字幕]EA使用SysML和Simulink的数字电子学仿真

DDD领域驱动设计批评文集>>

《软件方法》强化自测题集>>

《软件方法》各章合集>>

---

本文只提供字幕文件！

步骤1：

在SparxSystems官网下载教学视频和案例模型

https://sparxsystems.com/resources/webinar/release/ea152/simulation/matlab/introduction/matlab-digital.mp4

https://sparxsystems.com/resources/webinar/release/ea152/simulation/matlab/introduction/matlab-digital.feap

https://sparxsystems.com/resources/webinar/release/ea152/simulation/matlab/introduction/index.html

步骤2：

在UMLChina下载字幕文件

http://www.umlchina.com/tools/matlab-digital.srt

字幕文件内容由UMLChina记录并翻译

步骤3：

把字幕文件matlab-digital.srt和视频文件matlab-digital.mp4放在同一文件夹下

步骤4：

用支持字幕的播放器播放视频，例如VLC Player，不要用Windows自带的播放器。

---

0

00:00:00,010 --> 00:00:00,462

Hello
大家好

1

00:00:00,462 --> 00:00:02,951

this is Dermot O’Bryan from SparxSystems
我是SparxSystems的Dermot O’Bryan

2

00:00:02,951 --> 00:00:04,308

in this demonstration
在这个演示中【本中英字幕由UMLChina整理翻译】

3

00:00:04,308 --> 00:00:10,870

we will run over using the latest SysML options for simulating a digital electronic example in Simulink.
我们演示使用最新的SysML选项来仿真一个Simulink中的数字电路的例子。

4

00:00:11,210 --> 00:00:18,612

We’ll use the new SysPhS modeling to reference components that are defined in Simulink.
我们将使用新的SysPhS建模来引用Simulink中已定义的组件。

5

00:00:18,612 --> 00:00:23,136

For a quick overview of this topic, we’ll firstly have a broad look at setting up a digital model for Simulink,
为了快速了解本主题的概要，我们首先大致看看如何为Simulink设置一个数字模型，

6

00:00:23,136 --> 00:00:28,894

then we’ll look at using SysPhS patterns for creating predefined Simulink blocks.
然后使用SysPhS模式来创建预定义的Simulink块。

7

00:00:28,894 --> 00:00:31,567

In this exercise, we will use some predefined Simulink components,
在这个练习中，我们将使用一些预定义的Simulink组件，

8

00:00:31,567 --> 00:00:37,325

so we’ll look at how to model complex Simulink components in Enterprise Architect using SysPhS,
因此，我们会看看如何在Enterprise Architect使用SysPhS建模复杂的Simulink组件。

9

00:00:37,325 --> 00:00:41,437

then we will generate our Simulink model and run a simulation from this,
然后，我们生成Simulink模型，运行它的仿真，

10

00:00:41,437 --> 00:00:42,054

and finally
最后

11

00:00:42,054 --> 00:00:46,990

we’re looking to options for debugging any issue in the generated Simulink script
我们来看看调试所生成的Simulink脚本中问题的选项。

12

00:00:47,420 --> 00:00:48,295

for this example
本例中

13

00:00:48,295 --> 00:00:52,014

we are modeling a simple binary counter using flip flops
我们建模一个使用触发器的简单的二进制计数器

14

00:00:52,014 --> 00:00:56,828

but we will use it to provide a number of divisions of a clock frequency
但我们用它来提供时钟分频

15

00:00:56,828 --> 00:00:59,891

this type of frequency division was common inside
通俗一点说，这种类型的分频

16

00:00:59,891 --> 00:01:06,236

an early microprocessor where we had options for setting fast and slow clock speeds for the processor
在早期的微处理器很常见，可以用于设置处理器的时钟速度快慢

17

00:01:06,236 --> 00:01:16,300

so all we use is a digital square wave clock as an input and see how in our simulation in Simulink.
因此，我们使用一个数字方波时钟作为输入，看看Simulink中的仿真。

18

00:01:16,300 --> 00:01:18,270

the frequency output from each of the flip flops in the series hieressing the initial clock frequency
序列中每个触发器频率输出继承初始的时钟频率

19

00:01:18,810 --> 00:01:21,810

before we start creating diagrams and elements
在开始创建图形和元素之前

20

00:01:21,810 --> 00:01:22,810

we first of all
我们首先

21

00:01:22,810 --> 00:01:24,610

set our perspective to SysML
设置SysML的perspective

22

00:01:25,020 --> 00:01:32,950

this opens the model wizard. from this we can access some SysPhS foundation packages that we need to reference in the model
这里打开建模指南。从这里，我们可以访问一些需要在模型中引用的SysPhS基础包

23

00:01:33,970 --> 00:01:36,820

it is best to create a package to hold both
最好创建一个包来容纳它们

24

00:01:37,120 --> 00:01:41,114

Then select SysPhS and load the two libraries into the package in the browser
然后选择SysPhS，加载两个库到项目浏览器中的包

25

00:01:41,114 --> 00:01:41,780

26

00:01:42,900 --> 00:01:45,480

now let’s create a block definition diagram
现在，创建一个块定义图

27

00:01:49,320 --> 00:01:54,223

for the simulation we need to set up a reference to the SysPhS library
为了仿真，需要设置到SysPhS库的引用

28

00:01:54,223 --> 00:01:57,410

so we drag this library package onto the diagram
因此，把这个库的包拖到图上【本中英字幕由UMLChina整理翻译】

29

00:01:57,770 --> 00:02:02,630

we first set the package boundary on the block definition diagram to selectable
我们首先设置块定义图的包边界为selectable

30

00:02:05,380 --> 00:02:07,610

then from the package toolbox
然后，从包的工具箱

31

00:02:08,720 --> 00:02:13,260

we can create an import connector to reference the SysPhS packages
我们可以创建一个import连接器来引用该SysPhS包

32

00:02:18,450 --> 00:02:20,684

in terms of blocks for our model
针对模型中的块

33

00:02:20,684 --> 00:02:22,696

let’s start with a simplest
我们先从最简单的开始

34

00:02:22,696 --> 00:02:28,730

there is a SysPhS block for a Simulink constant that we use for setting a logical true state
这是一个SysPhS块，表达一个用于设置逻辑真状态的Simulink常数

35

00:02:29,010 --> 00:02:31,670

this can be accessed from the SysPhS patterns
这可以从SysPhS模式访问

36

00:02:37,860 --> 00:02:41,070

And the Sources and sinks, and the Constant
选Sources and sinks和Constant

37

00:02:46,500 --> 00:02:51,050

now all we want is a logical clock to get a digital pulse signal
现在我们需要一个逻辑时钟，以获得一个数字脉冲信号

38

00:02:51,560 --> 00:02:55,860

we select the SysPhS toolbox and drag on a Simulink Block
我们选择SysPhS工具箱，拖上来一个Simulink Block

39

00:02:57,230 --> 00:03:00,090

then we need to create another block for our flip flop
然后，需要为触发器创建另一个块

40

00:03:05,360 --> 00:03:08,740

All we want is a reference to a Simulink digital clock
需要引用到Simulink的数字时钟

41

00:03:09,020 --> 00:03:12,770

so let’s get the correct Simulink path for a digital clock
因此，先要取得正确的Simulink数字时钟路径

42

00:03:13,130 --> 00:03:15,470

this being a Simulink component
既然这是一个Simulink组件

43

00:03:15,470 --> 00:03:18,280

we find it in the Simulink Library Browser
可以在Simulink Library Browser里找

44

00:03:18,590 --> 00:03:22,224

you can see this under the Simulink Extras/Flip Flops
在Simulink Extras/Flip Flops下面

45

00:03:22,224 --> 00:03:22,830

46

00:03:23,570 --> 00:03:27,371

we open the parameters dialogue and work out the path
打开参数对话框，找到其路径

47

00:03:27,371 --> 00:03:30,630

this can be accessed using CTRL+L
可以用CTRL+L来访问

48

00:03:36,550 --> 00:03:37,515

in this case
本例中

49

00:03:37,515 --> 00:03:42,344

it is simulink_extras/Flip Flops/Clock
就是simulink_extras/Flip Flops/Clock

50

00:03:42,344 --> 00:03:43,310

51

00:03:44,020 --> 00:03:47,450

then we input that in the block in the SimulinkBlock name
然后我们把它输入到SimulinkBlock的名称中

52

00:03:59,320 --> 00:04:04,302

the earlier clock component that we need to use is also predefined in Simulink
之前需要使用的时钟组件也是在Simulink中预定义

53

00:04:04,302 --> 00:04:05,797

that is a flip flop
是一个触发器

54

00:04:05,797 --> 00:04:06,296

55

00:04:06,296 --> 00:04:08,040

Again, we get the path from Simulink
一样，我们从Simulink获得路径

56

00:04:08,450 --> 00:04:14,330

replaces in the name field on the flip flop block under the hitting SimulinkBlock
替换当前所点击的SimulinkBlock的名称栏

57

00:04:20,820 --> 00:04:28,435

the Simulink digital clock has one key parameter that we need to define as a PhS constant on the block
Simulink数字时钟有一个关键参数，我们需要定义为块上的PhS常数

58

00:04:28,435 --> 00:04:30,720

this is period and it’s of type time
该参数是时间周期，类型是时间

59

00:04:30,720 --> 00:04:32,750

which is in seconds
以秒为单位

60

00:04:32,750 --> 00:04:34,781

for this, we drag from the SysPhS toolbox a Simulink Parameter
因此，我们从SysPhS工具箱拖上来一个Simulink Parameter

61

00:04:34,781 --> 00:04:36,558

62

00:04:36,558 --> 00:04:37,320

we name it Period
命名为Period

63

00:04:41,360 --> 00:04:42,994

for the Period’s type which is time
因为Period的类型为时间

64

00:04:42,994 --> 00:04:49,260

use CTRL+L to set the classifier to Time in the SysPhS library
使用CTRL+L设置类元为SysPhS库中的Time

65

00:04:55,320 --> 00:04:58,860

for the time we can set this as a constant to 2
时间可以设置为一个常数2

66

00:04:58,860 --> 00:04:59,618

67

00:04:59,618 --> 00:05:00,630

for example half a HZ
例如，半HZ

68

00:05:00,630 --> 00:05:02,400

a period of 2 seconds
2秒的周期

69

00:05:02,400 --> 00:05:05,940

the first second is true the next second false or 0
第1秒为真，下一秒为假或0

70

00:05:06,220 --> 00:05:08,178

it also needs an output port
也需要一个输出端口

71

00:05:08,178 --> 00:05:12,340

this will need to be a port of type BooleanOutSignalElement
端口类型为BooleanOutSignalElement

72

00:05:12,620 --> 00:05:16,030

so we drag this from our package reference under the block
因此，我们从引用的包中把这个拖到块的下方

73

00:05:21,690 --> 00:05:23,760

then we name it as y
命名为y

74

00:05:26,990 --> 00:05:36,568

for the flip flop in Simulink, it has ports J K Q and CLK, so we need to set them up.
Simulink中的触发器有端口J、K、Q和CLK，因此我们需要设置它们

75

00:05:36,568 --> 00:05:42,617

note that these are Simulink components. these differ to the Modelica code world in that these ports are not identified by a name
注意，这是Simulink组件，和Modelica的代码有所不同，这些端口不是通过名称来标识

76

00:05:42,617 --> 00:05:45,390

rather a simply referenced by an array
而是通过array简单引用

77

00:05:45,670 --> 00:05:56,632

hence the ordering of the creation of these is critical.
the ordering in the Simulink array is from top to bottom for the inputs and top to bottom to the outputs
因此，创建的次序至关重要。Simulink array的次序，对输入是自顶而下，输出也是自顶而下

78

00:05:56,632 --> 00:05:58,915

so for your inputs to the J K flip flop
因此对于到J、K的输入

79

00:05:58,915 --> 00:06:01,199

it’s critical that we start with J
要从J开始

80

00:06:01,199 --> 00:06:01,884

Then do CLK
然后是CLK

81

00:06:01,884 --> 00:06:02,570

then do K
然后是K

82

00:06:02,950 --> 00:06:08,679

these are nonetheless shown in alphabetical order on the block.
尽管在块上是以字母顺序显示。

83

00:06:08,679 --> 00:06:14,000

we drag on the input ports. This is a BooleanInSignal and then name them to match these ports on the Simulink component
我们拖上来BooleanInSignal输入端口，让它的命名匹配Simulink组件的端口

84

00:06:48,180 --> 00:06:52,650

then we do the same for output ports using BooleanOutSignal
同样，用BooleanOutSignal对输出端口做同样的事情

85

00:06:52,930 --> 00:06:53,561

86

00:06:53,561 --> 00:06:55,456

Again, this is ordered by q
同样，顺序是q

87

00:06:55,456 --> 00:06:56,720

then qn
然后 qn

88

00:07:19,760 --> 00:07:21,085

in this section
在这一节

89

00:07:21,085 --> 00:07:25,060

we will create the main block that will contain the IBD diagram
我们将创建包含IBD图的块

90

00:07:25,340 --> 00:07:30,830

this new diagram is where we connect these ports as parts to form our flip flop counter
在这个新图中，我们把这些端口当成部件连接起来，形成触发器计数器

91

00:07:31,420 --> 00:07:34,260

now let’s create a block for the binary counter
现在来创建二进制计数器的块

92

00:07:34,940 --> 00:07:38,920

then we created a child diagram on this block called Counter
然后在这个块上面创建一张子图，称为Counter

93

00:07:45,340 --> 00:07:49,230

on which we then drag on our blocks as components
然后把我们的块作为组件拖上去

94

00:07:49,640 --> 00:07:50,176

95

00:07:50,176 --> 00:07:54,470

for this, it’s recommended to use the all option in the Paste dialogue
为此，推荐在Paste对话框中使用all选项

96

00:08:00,340 --> 00:08:02,570

to display these in the compartments
为了以分栏方式显示

97

00:08:02,850 --> 00:08:04,588

we delete the properties
我们删除属性

98

00:08:04,588 --> 00:08:07,320

the first is the clock period property
首先是时钟周期属性

99

00:08:08,080 --> 00:08:09,870

to keep the diagram clear
为了保持图形清爽

100

00:08:09,870 --> 00:08:15,914

we order the diagram properties to not show the port classifiers and the property types
我们设置图形的属性为不显示端口的类元和属性的类型

101

00:08:15,914 --> 00:08:18,600

this gives a simpler view of just the port name
只保留端口名称，看起来更简洁

102

00:08:25,150 --> 00:08:26,717

for our Constant part
对于Constant部件

103

00:08:26,717 --> 00:08:31,420

this needs to pass a logical 1 or true state to our j and k port
需要传送一个逻辑1或真给j和k端口

104

00:08:31,940 --> 00:08:34,490

we will set an appropriate name for this
给这个起一个恰当的名字

105

00:08:34,890 --> 00:08:34,891

106

00:08:34,891 --> 00:08:37,600

we also give the clock a more meaningful name
也给时钟一个更有意义的名字

107

00:08:42,370 --> 00:08:45,400

Then we create four parts of time flip flop
然后，创建4个时间触发器部件

108

00:09:00,790 --> 00:09:04,500

let’s name these as Flip Flop 1 to 4
命名为Flip Flop 1到4

109

00:09:14,510 --> 00:09:16,320

now we reorganize the ports
现在，重新组织端口

110

00:09:16,320 --> 00:09:18,810

placing the outgoing ports on the right
把输出端口放在右侧

111

00:09:25,130 --> 00:09:30,687

then we need to set our connectors between the relevant ports to fit our proposed model
然后我们需要设置相关端口之间的连接器，以匹配我们的模型

112

00:09:30,687 --> 00:09:35,390

the first is from the Clck output to the clock port on the first flip flop
第一个，从Clck输出到第一个触发器的时钟端口

113

00:09:35,670 --> 00:09:41,510

the subsequent flip flops are connected from the q to the proceeding clock import
随后的触发器从q连接到后续的时钟输入

114

00:09:44,640 --> 00:09:51,330

then we set the j and k ports to true by connecting this to the BoolTrue part
然后，通过把这个连接到BoolTrue部件，我们设置j和k端口为真

115

00:10:00,730 --> 00:10:01,072

OK

116

00:10:01,072 --> 00:10:03,810

that completes our IBD setup
这样就完成了IBD的设置

117

00:10:04,480 --> 00:10:06,810

let’s now configure our simulation
现在来配置仿真

118

00:10:07,090 --> 00:10:09,903

we go back to the block definition diagram
回到块定义图

119

00:10:09,903 --> 00:10:13,890

we see that we have a Counter block populated with the new parts
我们看到，Counter块添加了新的部件

120

00:10:14,260 --> 00:10:15,428

121

00:10:15,428 --> 00:10:19,870

for the simulation, we start by creating an artifact of type SysMLSim Configuration
首先，创建一个artifact，类型为SysMLSim Configuration

122

00:10:20,390 --> 00:10:24,440

double clicking on this opens up the simulation configuration
双击这个，打开仿真配置

123

00:10:25,200 --> 00:10:26,280

on opening this
打开这个

124

00:10:26,280 --> 00:10:29,250

we firstly select the package to simulate
首先选择要仿真的包

125

00:10:31,770 --> 00:10:34,600

ensure the Simulink library is referenced
确保Simulink库已被引用【本中英字幕由UMLChina整理翻译】

126

00:10:35,600 --> 00:10:41,650

set the parent block for the SysML model that we’re simulating, in this case is the counter block
设置正在仿真的SysML模型（本例为Counter块）的父块

127

00:10:41,930 --> 00:10:44,800

we set this a SysMLSimModel
把这个设为SysMLSimModel

128

00:10:45,460 --> 00:10:51,570

now we see the list of properties available to plot, so we can select which of these we want to use
现在可以看到可用于绘图的属性列表，我们可以选择要用到的

129

00:10:59,110 --> 00:11:01,240

now we can run the simulation
现在运行仿真

130

00:11:01,560 --> 00:11:03,810

the plot in Simulink is complex
Simulink的图很复杂

131

00:11:04,710 --> 00:11:06,950

so let’s simplify this
我们来简化一下

132

00:11:07,230 --> 00:11:10,657

in order to open the generated model in Simulink
为了在Simulink中打开所生成模型

133

00:11:10,657 --> 00:11:11,800

134

00:11:11,800 --> 00:11:12,485

135

00:11:12,485 --> 00:11:13,400

we access the EA generator and select file
我们访问EA生成器，选择文件

136

00:11:19,200 --> 00:11:22,862

here we can see the component that we created in the SysML model
这里我们可以看到在SysML模型中创建的组件

137

00:11:22,862 --> 00:11:23,293

138

00:11:23,293 --> 00:11:23,508

139

00:11:23,508 --> 00:11:23,939

140

00:11:23,939 --> 00:11:28,463

is shown in the Simulink format along with the connectivity that we set up in our SysML model
以及我们在SysML模型中设置的连接，以Simulink格式展示

141

00:11:28,463 --> 00:11:28,894

142

00:11:28,894 --> 00:11:29,110

143

00:11:29,590 --> 00:11:33,340

we can run this and view the plot and change all we want to view
我们可以运行这个，查看图表，改变想看的内容

144

00:11:39,950 --> 00:11:42,750

we start with the output of Flip Flop 1
从Flip Flop 1的输出开始

145

00:11:43,030 --> 00:11:45,001

then select the last output
然后选择最后一个输出

146

00:11:45,001 --> 00:11:46,410

which is q 4
即q 4

147

00:11:47,170 --> 00:11:48,638

with each q enabled
对于每个有效的q

148

00:11:48,638 --> 00:11:54,270

we see the simulation of the clock frequency being heard for each flip flop that is passed through
我们看到仿真，时钟频率被每个所通过的触发器接收到

149

00:12:00,960 --> 00:12:03,041

when doing a complex SysML model
当做一个复杂的SysML模型时

150

00:12:03,041 --> 00:12:06,070

there are bound to be issues with generation of the plot
图表的生成多半会出现问题

151

00:12:06,400 --> 00:12:07,259

so on that note
因此，这个地方

152

00:12:07,259 --> 00:12:12,415

let’s have a look at the debugging an issue resolution when generating the Simulink
我们来看看如何调试并解决生成Simulink时出现的问题

153

00:12:12,415 --> 00:12:12,630

154

00:12:12,980 --> 00:12:13,460

firstly
首先

155

00:12:13,460 --> 00:12:14,902

we set up an error
我们设置一个错误

156

00:12:14,902 --> 00:12:19,710

we do this by sending our wrong connectors to the block not to the port
我们把连接器连向块，而不是端口

157

00:12:28,630 --> 00:12:28,863

now
现在

158

00:12:28,863 --> 00:12:30,500

when we run the simulation
我们运行仿真时

159

00:12:30,500 --> 00:12:34,240

we can see that there is an error created in the code build, this is viewed in the System Output.
可以看到，构建代码时有一个错误，可以在System Output那里查看

160

00:12:35,060 --> 00:12:38,919

if we go to the SysML Simulation in the System Output
如果我们去往System Output中的SysML Simulation

161

00:12:38,919 --> 00:12:39,600

162

00:12:39,600 --> 00:12:39,827

163

00:12:39,827 --> 00:12:40,962

164

00:12:40,962 --> 00:12:43,460

we see the error that it is generated
可以看到生成的错误

165

00:12:43,820 --> 00:12:45,447

we double click on this
双击这个

166

00:12:45,447 --> 00:12:49,110

it opens a configuration at the port where the issue occurred
打开一个发生问题的端口的配置

167

00:12:49,440 --> 00:12:50,225

in this case
本例中

168

00:12:50,225 --> 00:12:54,150

we see that the clock is the part where the issue is
Clock是出问题的部件

169

00:12:55,010 --> 00:13:00,370

an alternative issue checking method is to open the generator script file directly in Simulink
另一个检查问题的方法是，直接在Simulink中打开生成器脚本文件

170

00:13:03,960 --> 00:13:06,770

then view the diagram and check the connection
然后观察图形，检查连接

171

00:13:07,160 --> 00:13:13,540

then you can run the simulation and view the error and see there is a connector issue
然后，运行仿真，观察错误，可以看到是连接器问题

172

00:13:20,970 --> 00:13:22,267

given this feedback
得到了这个反馈

173

00:13:22,267 --> 00:13:25,080

we can now do a simple correction of the model
就可以对模型做简单的修正

174

00:13:36,660 --> 00:13:36,906

OK

175

00:13:36,906 --> 00:13:38,137

176

00:13:38,137 --> 00:13:41,830

so in conclusion, let’s run over what we have covered in this demonstration
最后，归纳一下本演示的内容

177

00:13:42,110 --> 00:13:50,520

this includes setting up a digital logical model of Simulink by using SysPhS patterns for creating predefined Simulink blocks
包括：通过使用创建预定义Simulink块的SysPhS模式，来设置Simulink数字逻辑模型

178

00:13:51,360 --> 00:13:55,180

modeling other complex Simulink components using SysPhS
使用SysPhS建模其他复杂Simulink组件

179

00:13:55,500 --> 00:14:05,550

generating a Simulink model then simulating and viewing this in Simulink.
running over how to debug an issue and viewing the generated model in Simulink.
生成Simulink模型，仿真，在Simulink中查看，调试问题，
在Simulink中查看所生成模型

180

00:14:06,270 --> 00:14:09,817

although we have focused on using MATLAB Simulink
虽然我们聚焦于MATLAB Simulink

181

00:14:09,817 --> 00:14:15,020

please note that a Simulink scenario can be replicated using SysPhS for Modelica
但是，使用SysPhS for Modelica，Simulink的场景也可以照搬到Modelica

182

00:14:15,920 --> 00:14:23,350

hopefully this gives you a good starting point for getting familiar with the integration and simulation with MATLAB Simulink
希望这个演示能作为你熟悉与MATLAB Simulink集成和仿真的一个好起点

183

00:14:23,630 --> 00:14:26,942

this is all being part of the new SysML SysPhS features available in the Enterprise Architect 15.2
这都是Enterprise Architect 15.2新的SysML SysPhS特性的一部分

184

00:14:26,942 --> 00:14:27,218

185

00:14:27,218 --> 00:14:28,047

186

00:14:28,047 --> 00:14:28,875

187

00:14:28,875 --> 00:14:39,090

for more information on this, see sparxsystems.com/ea152
更多信息，参见sparxsystems.com/ea152【本中英字幕由UMLChina整理翻译】