one tip for HDL coding
In previos work, when I encounter the situation counter reach full state (such as counter[3:0] reaches 4'b1111), I used to manually flip counter to zeros on next rsing clock edge . However, I have ignored the fact that counter will automatically overflow on next rising clock edge when it reaches full state.
Codes below are part of synchronous FIFO design, I will release the rest when I finish testing.
Previous coding style
1
begin
2
if
(wr_addr
!=
4
'
b1111)
3
begin
4
if
(rd_addr
!=
wr_addr
+
4
'
b0001)
5
ns
=
wcntstate;
6
else
7 ns
=
fullstate;
8
end
9
else
10
begin
11
if
(rd_addr
!=
4
'
b0000)
12
ns
=
wcntstate;
13
else
14 ns
=
fullstate;
15
end
16
end
begin
2
if
(wr_addr
!=
4
'
b1111)
3
begin
4
if
(rd_addr
!=
wr_addr
+
4
'
b0001)
5
ns
=
wcntstate;6
else
7
ns
=
fullstate;8
end
9
else
10
begin
11
if
(rd_addr
!=
4
'
b0000)
12
ns
=
wcntstate;13
else
14
ns
=
fullstate;15
end
16
end
modified coding style
1
begin
2
if
(wr_addr
!=
rd_addr
+
4
'
b0001)
3
ns
=
wcntstate;
4
else
5 ns
=
emptystate;
6
end
begin
2
if
(wr_addr
!=
rd_addr
+
4
'
b0001)
3
ns
=
wcntstate;4
else
5
ns
=
emptystate;6
end