【Verilog语法002】generate for / if / case语句

/
genvar	i;		    //利用genvar声明正整数变量
generate for(i=0;i<;i=+1)//复制模块
	begin : gfor    //begi_end的名字
		assign temp[i] = data_in[2*i+1:2*i]; 
	end
endgenerate
/
localparam    S = 6;//定义模块所需参数,用于判断产生电路
generate 
	if(S < 7)		
		assign d = t0 | t1 | t2;
	else
		assign d = t0 & t1 & t2;
endgenerate
/
localparam    S = 8;//定义模块所需参数,用于判断产生电路
generate 
	case(S)
	0:
		assign d = t0 | t1 | t2;
	1:
		assign d = t0 & t1 & t2;
	default:
		assign d = t0 & t1 | t2;
	endcase
endgenerate