vivado PLL调用

顶层

module ip_clk_wiz (
    // input
    input sys_clk,
    input sys_rst_n,
    
    // output
    output clk_100m,
    output clk_100m_180deg,
    output clk_50m,
    output clk_25m
);
wire locked;


  clk_wiz_0 clk_wiz_0_inst0
   (
    // Clock out ports
    .clk_out1(clk_100m),     // output clk_out1
    .clk_out2(clk_100m_180deg),     // output clk_out2
    .clk_out3(clk_50m),     // output clk_out3
    .clk_out4(clk_25m),     // output clk_out4
    // Status and control signals
    .reset(~sys_rst_n), // input reset
    .locked(locked),       // output locked
   // Clock in ports
    .clk_in1(sys_clk));      // input clk_in1

endmodule

schematic

 

testbench

`timescale 1ns/1ns

module tb_ip_clk_wiz();
reg sys_clk;
reg sys_rst_n;

wire clk_100m;
wire clk_100m_180deg;
wire clk_50m;
wire clk_25m;
// wire locked;
initial begin
    sys_clk = 1'b0;
    sys_rst_n = 1'b0;
    #200
    sys_rst_n = 1'b1;
    #400
    $display("run testbench");
    $stop;
end

always #10 sys_clk = ~sys_clk;
//instance
ip_clk_wiz ip_clk_wiz_inst0(
    //input
    .sys_clk(sys_clk),
    .sys_rst_n(sys_rst_n),

    // output
    .clk_100m(clk_100m),
    .clk_100m_180deg(clk_100m_180deg),
    .clk_50m(clk_50m),
    .clk_25m(clk_25m)
);

/**
module ip_clk_wiz (
    // input
    input sys_clk,
    input sys_rst_n,
    
    // output
    output clk_100m,
    output clk_100m_180deg,
    output clk_50m,
    output clk_25m
);
*/ 
endmodule

 simulation

just for record.