vivado：引脚已约束但是报错

一、问题引入

报错信息如下：

[DRC UCIO-1] Unconstrained Logical Port: 3 out of 3 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: CpSl_GlbClk_iN, CpSl_GlbClk_iP, and CpSl_GlbRst_iN.

报错信息里说没有约束引脚，但实际上这三个引脚都约束了的，不知道为什么还报错。

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二、解决方法

根据报错信息中给的提示：

1. 新建一个tcl文件

在里面写入：set_property SEVERITY {Warning} [get_drc_checks UCIO-1]，然后保存

2. 把tcl文件添加到 Generate Bitstream -> Bitstream Settings -> tcl.pre*

鼠标点到Generate Bitstream ，然后右键，出现Bitstream Settings，点击进入，在tcl.pre*中添加新建好的tcl文件。

完成以上步骤后，重新生成比特文件就不会报错了。