组合逻辑电路-multiplexer多路复用器

Create a one-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module( 
    input a, b, sel,
    output out ); 
assign out = sel?b:a;
endmodule

Create a 100-bit wide, 2-to-1 multiplexer. When sel=0, choose a. When sel=1, choose b.

module top_module( 
    input [99:0] a, b,
    input sel,
    output [99:0] out );
	assign out = sel?b:a;
endmodule

Create a 16-bit wide, 9-to-1 multiplexer. sel=0 chooses a, sel=1 chooses b, etc. For the unused cases (sel=9 to 15), set all output bits to '1'. 

module top_module( 
    input [15:0] a, b, c, d, e, f, g, h, i,
    input [3:0] sel,
    output [15:0] out );
 always @(*) begin 
     case(sel) 
         4'd0: out = a; 
         4'd1: out = b; 
         4'd2: out = c; 
         4'd3: out = d; 
         4'd4: out = e; 
         4'd5: out = f; 
         4'd6: out = g; 
         4'd7: out = h; 
         4'd8: out = i; 
         default:out = 16'hffff; 
     endcase 
 end
endmodule

way2
module top_module (
	input [15:0] a,
	input [15:0] b,
	input [15:0] c,
	input [15:0] d,
	input [15:0] e,
	input [15:0] f,
	input [15:0] g,
	input [15:0] h,
	input [15:0] i,
	input [3:0] sel,
	output logic [15:0] out
);

	// Case statements can only be used inside procedural blocks (always block)
	// This is a combinational circuit, so use a combinational always @(*) block.
	always @(*) begin
		out = '1;		// '1 is a special literal syntax for a number with all bits set to 1.
						// '0, 'x, and 'z are also valid.
						// I prefer to assign a default value to 'out' instead of using a
						// default case.
		case (sel)
			4'h0: out = a;
			4'h1: out = b;
			4'h2: out = c;
			4'h3: out = d;
			4'h4: out = e;
			4'h5: out = f;
			4'h6: out = g;
			4'h7: out = h;
			4'h8: out = i;
		endcase
	end
endmodule

 Create a 1-bit wide, 256-to-1 multiplexer. The 256 inputs are all packed into a single 256-bit input vector. sel=0 should select in[0], sel=1 selects bits in[1], sel=2 selects bits in[2], etc.

With this many options, a case statement isn't so useful.
Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. In particular, selecting one bit out of a vector using a variable index will work.

有了这么多选项，case语句就没那么有用了。

矢量索引可以是可变的，只要合成器能够计算出所选位的宽度是恒定的。特别是，使用可变索引从向量中选择一位将起作用

module top_module( 
    input [255:0] in,
    input [7:0] sel,
    output out );
    assign out = in[sel];
endmodule

Create a 4-bit wide, 256-to-1 multiplexer. The 256 4-bit inputs are all packed into a single 1024-bit input vector. sel=0 should select bits in[3:0], sel=1 selects bits in[7:4], sel=2 selects bits in[11:8], etc.

With this many options, a case statement isn't so useful.
Vector indices can be variable, as long as the synthesizer can figure out that the width of the bits being selected is constant. It's not always good at this. An error saying "... is not a constant" means it couldn't prove that the select width is constant. In particular, in[ sel*4+3 : sel*4 ] does not work.
Bit slicing ("Indexed vector part select", since Verilog-2001) has an even more compact syntax.

有了这么多选项，case语句就没那么有用了。

矢量索引可以是可变的，只要合成器能够计算出所选位的宽度是恒定的。它并不总是擅长这个。“不是常量”的错误表示无法证明“选择宽度”是常量。特别是，In[sel*4+3:sel*4]不起作用。

module top_module( 
    input [1023:0] in,
    input [7:0] sel,
    output [3:0] out );
    assign out={in[sel*4+3],in[sel*4+2],in[sel*4+1],in[sel*4]};
endmodule