Thumb-2指令集是ARM公司在ARMv6版本中推出的一种指令集,它提供了一种通用32位指令和一些16位指令的混合形式。通过使用16位指令,Thumb-2指令集可以减少程序占用的存储空间并提高代码密度,同时还可以提高处理器的性能。而通过使用32位指令,Thumb-2指令集可以支持更加复杂的操作和更高的精度,满足不同应用场景的需求。
AND: AND r0, r1, #255 ; R0 = R1 & 255 与
EOR: EOR r0, r1, r2 ; R0 = R1 ^ R2 异或:对两个二进制数的每一位进行比较,如果相同则返回0,不同则返回1
SUB: SUB r0, r1, #10 ; R0 = R1 - 10
RSB: RSB r0, r1, #100 ; R0 = 100 - R1
ADD: ADD r0, r1, #20 ; R0 = R1 + 20
ADC: ADC r0, r1, r2 ; R0 = R1 + R2 + C 进位标志位C,需要和别的指令组合使用,例如十进制 5 + 6 = 11 会进以为,C就是1
SBC: SBC r0, r1, r2 ; R0 = R1 - R2 - !C 进位标志位C,需要和别的指令组合使用
RSC: RSC r0, r1, r2 ; R0 = R2 - R1 - !C
TST: TST r0, r1 ; Set CPSR flags based on R0 & R1
TEQ: TEQ r0, r1 ; Set CPSR flags based on R0 ^ R1
CMP: CMP r0, r1 ; Set CPSR flags based on R0 - R1
CMN: CMN r0, r1 ; Set CPSR flags based on R0 + R1
ORR: ORR r0, r1, #64 ; R0 = R1 | 64
MOV: MOV r0, r1 ; R0 = R1
BIC: BIC r0, r1, #4 ; R0 = R1 & ~4
MVN: MVN r0, r1 ; R0 = ~R1
B: B label ; Branch to the label
BL: BL label ; Branch with link to the label
BX: BX r0 ; Branch to address in R0
BLX: BLX r0 ; Branch with link to address in R0
LDR: LDR r0, [r1] ; R0 = [R1] 把 R1 里面的值取出来,加载到R0里面,R1 相当于一个指针,对指针取值操作,load进R0,即赋值给R0
LDR R0, =__main ; 将代码段中标记为__main的地址加载到寄存器R0中,在ARM汇编语言中,= 符号用于表示“伪指令”,即由编译器在编译期间处理的伪指令
BX R0 ; 然后跳转到R0 处执行函数调用,也就是调用函数 __main, 然后后面会调用 主函数 main函数
STR: STR r0, [r1] ; [R1] = R0
LDRB: LDRB r0, [r1] ; R0 = [R1] (byte)
STRB: STRB r0, [r1] ; [R1] = R0 (byte)
LDRH: LDRH r0, [r1] ; R0 = [R1] (halfword)
STRH: STRH r0, [r1] ; [R1] = R0 (halfword)
LDM: LDMIA r0!, {r1, r2, r3} ; load multiple registers from memory and increment
STM: STMIA r0!, {r1, r2, r3} ; store multiple registers to memory and increment
LDMEA: LDMEQIA r0!, {r1, r2, r3} ; load multiple registers from memory if CPSR flags match and increment
STMEA: STMEQIA r0!, {r1, r2, r3} ; store multiple registers to memory if CPSR flags match and increment
PUSH: PUSH {r0, r1, r2} ; push multiple registers onto stack
POP: POP {r0, r1, r2} ; pop multiple registers from stack
SVC: SVC #0 ; Call supervisor mode with parameter 0
BKPT: BKPT #0 ; Enter debug mode
HVC: HVC #0 ; Call hypervisor mode with parameter 0
SMC: SMC #0 ; Call secure monitor mode with parameter 0
IT: ITE EQ ; Start an if-then-else block based on CPSR flags
ADDW: ADDW r0, r1, #500 ; R0 = R1 + 500 (32-bit)
SUBW: SUBW r0, r1, #1000 ; R0 = R1 - 1000 (32-bit)
MOVW: MOVW r0, #0xFF000000 ; R0 = 0xFF000000 (32-bit)
LDRD: LDRD r0, r1, [r2] ; Load a doubleword from memory into R0 and R1
STRD: STRD r0, r1, [r2] ; Store a doubleword from R0 and R1 to memory
DMB: DMB ; Data Memory Barrier
DSB: DSB ; Data Synchronization Barrier
ISB: ISB ; Instruction Synchronization Barrier
MRS: MRS r0, CPSR ; Move CPSR register to R0
MSR: MSR CPSR_f, #0 ; Move value 0 into a specific CPSR flag
CDP: CDP p1, 0, c0, c0, 0, 0 ; Co-processor data processing
LDC: LDC p1, c1, [r0, #32] ; Load co-processor registers from memory
STC: STC p1, c1, [r0, #32] ; Store co-processor registers to memory
MCRR: MCRR p1, 0, r0, r1, c0 ; Move co-processor registers to two ARM registers
MRRC: MRRC p1, 0, r0, r1, c0 ; Move two ARM registers to co-processor registers
MCR: MCR p1, 0, r0, c0, c1, 0 ; Move data from an ARM register to a co-processor register
MRC: MRC p1, 0, r0, c0, c1, 0 ; Move data from a co-processor register to an ARM register
NOP: NOP ; No operation
SEV: SEV ; Send event
WFE: WFE ; Wait for event
WFI: WFI ; Wait for interrupt
YIELD: YIELD ; Yield execution