HDLBits笔记5:Circuits.Combinational Logic.Basic gates
Wire
实现一个电路完成in和out的连线
module top_module (input in, output out);
assign out = in;
endmodule
GND
实现一个电路将out连到GND
module top_module (output out);
assign out = 1'b0;
endmodule
NOR
实现或非门
module top_module (
input in1,
input in2,
output out);
assign out = ~(in1 | in2);
endmodule
Another Gate
实现如下电路
module top_module (
input in1,
input in2,
output out);
assign out = in1 & ~in2;
endmodule
Two Gates
实现如下电路
module top_module (
input in1,
input in2,
input in3,
output out);
assign out = (in1 ^~ in2) ^ in3;
endmodule
More logic gates
实现与、或、异或、与非、或非、同或、a与b非
module top_module(
input a, b,
output out_and,
output out_or,
output out_xor,
output out_nand,
output out_nor,
output out_xnor,
output out_anotb
);
assign out_and = a & b;
assign out_or = a | b;
assign out_xor = a ^ b;
assign out_nand = ~(a & b);
assign out_nor = ~(a | b);
assign out_xnor = ~(a ^ b);
assign out_anotb = a & ~b;
endmodule
7420 chip
实现如下电路
module top_module (
input p1a, p1b, p1c, p1d,
output p1y,
input p2a, p2b, p2c, p2d,
output p2y );
assign p1y = ~(p1a & p1b & p1c & p1d);
assign p2y = ~(p2a & p2b & p2c & p2d);
endmodule
Truth table
| x3 | x2 | x1 | f |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 0 |
| 0 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 |
| 1 | 1 | 1 | 1 |
实现上述真值表
module top_module(
input x3,
input x2,
input x1, // three inputs
output f // one output
);
assign f = (~x1 & x2 & ~x3) | (x1 & x2 & ~x3) | (x1 & ~x2 & x3) | (x1 & x2 & x3);
endmodule
Two-bit equality
实现一个2bit的等于比较器
module top_module ( input [1:0] A, input [1:0] B, output z );
assign z = A == B;
endmodule
Simple circuit A
实现一个电路完成z = (x^y) & x功能
module top_module (input x, input y, output z);
assign z = (x ^ y) & x;
endmodule
Simple circuit B
实现电路，波形如下：
module top_module ( input x, input y, output z );
assign z = x ^~ y;
endmodule
Combine circuits A and B
实现如下电路，其中A为上面的Simple circuit A，B为Simple circuit B
module top_module (input x, input y, output z);
wire z1, z2;
assign z1 = x & ~y;
assign z2 = x ^~ y;
assign z = (z1 | z2) ^ (z1 & z2);
endmodule
Ring or vibrate
假设你在控制一个手机的铃声和振动，当电话打来(input ring)时，你必须响铃(output ringer = 1)或振动(output motor = 1)，但不能同时响铃和振动，如果手机处于振动模式(input vibrate_mode = 1)，则振动，否则响铃
module top_module (
input ring,
input vibrate_mode,
output ringer, // Make sound
output motor // Vibrate
);
assign ringer = vibrate_mode ? 1'b0 : ring;
assign motor = vibrate_mode ? ring : 1'b0;
endmodule
Thermostat
温度调节器内既有加热器也有制冷器，温度调节器有两个状态：加热模式(mode = 1)、制冷模式(mode = 0)。在加热模式，当太冷时(too_cold = 1)，打开加热器，在制冷模式，当太热时(too_hot = 1)，打开制冷器。不管是打开加热器还是制冷器，都要打卡风扇，同时，用户可以自行打开风扇(fan_on = 1)，即使加热器和制冷器都没打开。
试着尽可能只用assign语句完成该模块
module top_module (
input too_cold,
input too_hot,
input mode,
input fan_on,
output heater,
output aircon,
output fan
);
assign heater = mode ? too_cold : 1'b0;
assign aircon = mode ? 1'b0 : too_hot;
assign fan = fan_on ? 1'b1 : (heater | aircon);
endmodule
3-bit population count
计算3bit输入中有多少个1
module top_module(
input [2:0] in,
output [1:0] out );
assign out = in[2] + in[1] + in[0];
endmodule
Gates and vectors
输入4bit信号in，输出out_both、out_any、out_different
-
out_both: in的每bit和其左邻如果都为1，则该bit的output为1
举例：如果in[2]和in[3]为1，则out_both[2]为1，in[3]没有左邻，所以没有out_both[3]
-
out_any: in的每bit和其右邻如果有至少一个1，则该bit的output为1
举例：如果in[2]和in[1]有至少一个1，则out_any[2]为1，in[0]没有右邻，所以没有out_both[0]
-
out_different: in的每bit和其左邻如果不同，则该bit的output为1
举例：如果in[2]和in[3]不同，则out_different[2]为1，MSB的左邻为LSB
module top_module(
input [3:0] in,
output [2:0] out_both,
output [3:1] out_any,
output [3:0] out_different );
// 方法一：逻辑门+位拼接
assign out_both = {in[3] & in[2], in[2] & in[1], in[1] & in[0]};
assign out_any = {in[3] | in[2], in[2] | in[1], in[1] | in[0]};
assign out_different = {in[0] ^ in[3], in[3] ^ in[2], in[2] ^ in[1], in[1] ^ in[0]};
/* 方法二：位选
assign out_any = in[3:1] | in[2:0];
assign out_both = in[2:0] & in[3:1];
assign out_different = in ^ {in[0], in[3:1]};
*/
endmodule
Even longer vectors
原理同上Gates and vectors，但输入为100bit位宽
module top_module(
input [99:0] in,
output [98:0] out_both,
output [99:1] out_any,
output [99:0] out_different );
assign out_both = in[99:1] & in[98:0];
assign out_any = in[99:1] | in[98:0];
assign out_different = in ^ {in[0], in[99:1]};
endmodule