编写一个有32个32位寄存器的寄存器堆

使用verilog HDL进行编写

module regfile(rna,rnb,d,wn,we,clk,clrn,qa,qb);
input [4:0] rna,rnb,wn;
input [31:0] d;
input we,clk,clrn;
output [31:0] qa,qb;
reg[31:0] register [1:31];// r1-r31 regs
//2 read port
assign qa=(rna==0)?0: register[rna];// read port 0
assign qb=(rnb==0)? 0:register[rnb]; // read port 1
//1 write port
always @(posedge clk or negedge clrn)
if (clrn ==0) begin
integer i;
for (i=1; i<32;i=i+1)
register[i]<=0;
end else
// write port
if (we &&(wn !=0))
register[wn]<=d;
endmodule