第四章初始化（Cortex-M7 Processor）

目录

第4章初始化

4.1关于初始化

4.4.1初始化主控板

4.1.2初始化FPU

4.1.3初始化并启用L1缓存

4.1.4禁用缓存错误检查和纠正

4.1.5启用TCM

4.1.6预加载TCM

4.1.7开启TCM的retry和read-modify-write功能

4.1.8使能AHBP接口

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第4章初始化

本章描述如何初始化处理器，以及在使用处理器特性之前访问哪些寄存器以启用功能。

它包含以下部分:

4-2页面中的“关于初始化”。

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4.1关于初始化

在运行应用程序之前，您可能需要:

• 将特定的值输入到不同的寄存器中，例如堆栈指针。
• 启用各种处理器功能，例如，纠错。
• 将特定值编程到内存中，例如，紧耦合内存(TCMs)。

其他初始化要求见:

• 初始化主控板。
• 初始化FPU。
• 初始化并启用第4-3页中的LI缓存。
• 关闭4-4页的缓存错误检查和更正。
• 在4-4界面启动TCM。
• 在4-5页预加载TCM。
• 在4-5界面开启TCM的retry和read-modify-write功能。
• 在4-6页启用AHBP接口

初始化的一些要求是可选的，具体取决于Cortex-M7处理器中实现的特性。

请注意

分支预测器总是在处理器中启用，因此是CCR。BP为RAO/WI。有关配置和控制寄存器的更多信息，请参阅Armv7-M架构参考手册。

4.4.1初始化主控板

如果处理器已经实现了内存保护单元(MPU)，在您可以使用它之前，您必须在MPU_CTRL寄存器中启用MPU。有关更多信息，请参阅Arm v7-M架构参考手册。在设置MPU时，如果MPU先前已被编程，请禁用未使用的区域，以防止任何先前的区域设置影响新的MPU设置。

4.1.2初始化FPU

如果处理器使用浮点单元(FPU)实现，则必须在执行浮点指令之前启用它。下面的代码是如何启用该特性的示例。

CPACR eqe000ed88

ldr0 =CPACR

LDR r1， [RO]    ;读CPACR

ORR r1, r1， #(0xF << 20)          ;设置位20-23使能CP10和CP11协处理器

STR r1， [R0]        ;将修改后的值回写到CPACR

DSB

ISB

有关更多信息，请参阅Arm v7-M架构参考手册。

请注意

浮点逻辑仅适用于带有FPU的Cortex-M7处理器。

4.1.3初始化并启用L1缓存

如果处理器是用L1数据或指令缓存实现的，那么它们必须是在软件中启用它们之前使其无效，否则会发生不可预测的行为。

示例1：使整个数据缓存无效

Software can use the following code example to invalidate the entire data cache,
if it has been included in the processor. The operation is carried out by iterating
over each line of the cache and using the DCISW register in the Private
Peripheral Bus (PPB) memory region to invalidate the line. The number of cache
ways and sets is determined by reading the CCSIDR register.
CCSIDR EQU 0xE000ED80 ; Cache size ID register address
CSSELR EQU 0xE000ED84 ; Cache size selection register address
DCISW EQU 0xE000EF60 ; Cache maintenance op address: data cache clean and invalidate by set/way
; CSSELR selects the cache visible in CCSIDR
MOV r0, #0x0 ; 0 = select “level 1 data cache”
LDR r11, =CSSELR ;
STR r0, [r11] ;
DSB ; Ensure write to CSSELR before proceeding
LDR r11, =CCSIDR ; From CCSIDR
LDR r2, [r11] ; Read data cache size information
AND r1, r2, #0x7 ; r1 = cache line size
ADD r7, r1, #0x4 ; r7 = number of words in a cache line
UBFX r4, r2, #3, #10 ; r4 = number of “ways”-1 of data cache
UBFX r2, r2, #13, #15 ; r2 = number of “set”-1 of data cache
CLZ r6, r4 ; calculate bit offset for “way” in DCISW
LDR r11, =DCISW ; invalidate cache by set/way
inv_loop1 ; For each “set”
MOV r1, r4 ; r1 = number of “ways”-1
LSLS r8, r2, r7 ; shift “set” value to bit 5 of r8
inv_loop2 ; For each “way”
LSLS r3, r1, r6 ; shift “way” value to bit 30 in r6
ORRS r3, r3, r8 ; merge “way” and “set” value for DCISW
STR r3, [r11] ; invalidate D-cache line
SUBS r1, r1, #0x1 ; decrement “way”
BGE inv_loop2 ; End for each “way”
SUBS r2, r2, #0x1 ; Decrement “set”
BGE inv_loop1 ; End for each “set”
DSB ; Data sync barrier after invalidate cache
ISB ; Instruction sync barrier after invalidate cache

示例2：使指令缓存无效

You can use the following code example to invalidate the entire instruction cache,
if it has been included in the processor. The operation is carried out by writing to
the ICIALLU register in the PPB memory region.
ICIALLU EQU 0xE000EF50
MOV r0, #0x0
LDR r11, =ICIALLU
STR r0, [r11]
DSB
ISB

示例3：启用数据和指令缓存

You can use the following code example to enable the data and instruction cache
after they have been initialized. The operation is carried out by modifying the
CCR.IC and CCR.DC fields in the PPB memory region.
CCR EQU 0xE000ED14
LDR r11, =CCR
LDR r0, [r11]
ORR r0, r0, #0x1:SHL:16 ; Set CCR.DC field
ORR r0, r0, #0x1:SHL:17 ; Set CCR.IC field
STR r0, [r11]
DSB
ISB

4.1.4禁用缓存错误检查和纠正

If cache error checking and correction is included in the processor it is enabled by default from
reset. The following code example can be used to disable the feature. The operation is carried
out by modifying the CM7_CACR.ECCEN bit the PPB memory region.
CM7_CACR EQU 0xE000EF9C
LDR r11, =CM7_CACR
LDR r0, [r11]
BFC r0, #0x1, #0x1 ; Clear CM7_CACR.ECCEN
STR r0, [r11]
DSB
ISB
Care must be taken when software changes the error checking fields in the CM7_CACR. If the
fields are changed when the caches contain data, ECC information in the caches might not be
correct for the new setting, resulting in unexpected errors and data loss. Therefore the fields in
the CM7_CACR must only be changed when both caches are turned off and the entire cache
must be invalidated after the change.

4.1.5启用TCM

The TCM interfaces can be enabled at reset in the system by an external signal on the processor.
If they are disabled at reset then the following code example can be used to enable both the
instruction and data TCM interfaces in software:
CM7_ITCMCR EQU 0xE000EF90
CM7_DTCMCR EQU 0xE000EF94
LDR r11, =CM7_ITCMCR
LDR r0, [r11]
ORR r0, r0, #0x1 ; Set CM7_ITCMCR.EN field
STR r0, [r11]
LDR r11, =CM7_DTCMCR
LDR r0, [r11]
ORR r0, r0, #0x1 ; Set CM7_DTCMCR.EN field
STR r0, [r11]
DSB
ISB

4.1.6预加载TCM

预加载TCM的方法包括：

• 带有运行引导代码的内存副本

如果引导代码包含从ROM读取数据并将其写入相应TCM的内存复制例程，则必须使TCM能够执行此操作。这个引导码必须从TCM区域以外的地址运行。

• DMA入TCM

系统包括一个DMA设备，它从ROM中读取数据，并通过AHB从接口将数据写入TCM。此方法可用于预加载TCM，以便它们可以在复位时被处理器使用。

• 使用重启后的TCM

如果将TCM接口配置为重启时使能TCM，且复位向量地址在TCM内存区域内，则处理器将从TCM启动。在执行开始之前，系统必须确保引导码软件存在于适当的内存区域中。这可以通过在复位前初始化内存或在复位后使用AHB从接口传输数据并断言CPUWAIT输入信号来实现。断言此信号将停止处理器在复位后获取或执行指令。当CPUWAIT信号解除时，处理器开始以正常方式从复位向量地址获取指令。

请注意当CPUWAIT被解除，开始取处理器时。CPUWAIT不能再次断言，除非处理器处于处理器复位或上电复位状态;即断言了nSYSRESET或nPORESET。如果CPUWAIT在处理器运行时被断言，处理器不会停止。

4.1.7开启TCM的retry和read-modify-write功能

If the TCM connected to the processor supports error detection and correction then the TCM
interface must be configured to support the retry and read-modify-write features. These can be
enabled at reset in the system by external signals on the processor. If they are disabled at reset
then the following code example can be used to enable them in software:
CM7_ITCMCR EQU 0xE000EF90
CM7_DTCMCR EQU 0xE000EF94
LDR r11, =CM7_ITCMCR
LDR r0, [r11]
ORR r0, r0, #0x1:SHL:1 ; Set CM7_ITCMCR.RMW field
ORR r0, r0, #0x1:SHL:2 ; Set CM7_ITCMCR.RETEN field
STR r0, [r11]
LDR r11, =CM7_DTCMCR
LDR r0, [r11]
ORR r0, r0, #0x1:SHL:1 ; Set CM7_DTCMCR.RMW field
ORR r0, r0, #0x1:SHL:2 ; Set CM7_DTCMCR.RETEN field
STR r0, [r11]
DSB
ISB

4.1.8使能AHBP接口

The AHBP interface can be enabled at reset in the system by an external signal on the processor.
If it is disabled at reset then the following code example can be used to enable the AHBP
interface from software:
CM7_AHBPCR EQU 0xE000EF98
LDR r11, =CM7_AHBPCR
LDR r0, [r11]
ORR r0, r0, #0x1 ; Set CM7_AHBPCR.EN field
STR r0, [r11]
DSB
ISB