请问一下我怎么在慢时钟域采到快时钟的10个脉冲呢？我自己做了脉冲延拓和打拍处理但是只采到4个脉冲呢？——疑惑求解答

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2023/07/29 09:35:32
// Design Name: 
// Module Name: top
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//


module top
(
input clk_50m,
input key4


    );
	
	reg reg1  ;
	reg reg2  ;
	wire w_key;
	
	
	wire clk_200m;
	wire clk_25m;
	wire locked;
	
	reg w_cak;
	reg [11:0]cnt0;
	reg [5:0]cnt1;
	
	reg pp_start;
	reg [11:0]cnt2;
	
	
	
	
	
	
	
	
assign 	w_key=reg2;
	
	
always@(posedge clk_50m )	
begin
	reg1<=key4;
	reg2<=reg1;
end		
	
	
	
	//蹇椂閽熷埌鎱㈡椂閽熷鐞?

	reg reg3  ;
	reg reg4  ;
	reg reg5  ;
    reg reg6  ;
	
	
	wire w1_w_cak;
	wire w_w_cak;

	assign w_w_cak=w_cak|reg3|reg4;
    assign 	w1_w_cak=reg6;

always@(posedge clk_200m )	
begin
	reg3<=w_cak;
	reg4<=reg3;
end	





	
	
always@(posedge clk_25m )	
begin
	reg5<=w_w_cak;
	reg6<=reg5;
end		
	





	
	
	
	
	
	
	
	
	 clk_wiz_0 u_clk_wiz_0                       
  (                                            
   // Clock out ports                          
   .clk_out1(clk_200m),     // output clk_out1 
   .clk_out2(clk_25m),     // output clk_out2 
   // Status and control signals               
   .reset(~w_key), // input reset               
   .locked(locked),       // output locked     
  // Clock in ports                            
   .clk_in1(clk_50m));      // input clk_in1   
	
	
	
always@(posedge clk_200m or negedge locked)	
begin
	if(locked==1'd0)
		begin
			w_cak<=1'd0;
			cnt0<=12'd0;
		end	
	else if(cnt1<5'd10)	
		begin		
			if(cnt0==12'd500)	
				begin	
					w_cak<=1'd1;	
					cnt0<=12'd0;	
				end						
			else	
				begin	
					w_cak<=1'd0;	
					cnt0<=cnt0+12'd1;	
				end	
		end				
	else
		begin
			w_cak<=1'd0;
			cnt0<=12'd0;
		end	
end		
		
		
		

always@(posedge clk_200m or negedge locked)	
begin
	if(locked==1'd0)
		begin
			cnt1<=6'd0;			
		end	
	else if(cnt0==12'd500)
		begin						
			cnt1<=cnt1+6'd1;
		end					
	else
		begin
			cnt1<=cnt1;
		end	
end






always@(posedge clk_25m or negedge locked)	
begin
	if(locked==1'd0)
		begin
			pp_start<=1'd0;			
		end	
	else if(w1_w_cak==1'd1)
		begin						
			pp_start<=1'd1;
			
		end	
	else if(cnt2>12'd300)	
		pp_start<=1'd0;			
		
		
	else
		begin
			pp_start<=pp_start;
		end	
end



always@(posedge clk_25m or negedge locked)	
begin
	if(locked==1'd0)
		begin
			cnt2<=12'd0;			
		end	
	else if(pp_start==1'd1)
		begin
			if(w1_w_cak==1'd1)
				begin						
					cnt2<=12'd0;					
				end										
			else
				begin
					cnt2<=cnt2+12'd1;
				end	
		end	
	else	
		begin
			cnt2<=cnt2;
		end									
end























ila_0 u_ila_0 (
	.clk(clk_200m), // input wire clk


	.probe0({clk_50m,clk_25m,w_cak,locked,cnt0,cnt1,pp_start,cnt2,reg3,reg4,w_w_cak,reg5,reg6,w1_w_cak}) // input wire [49:0] probe0
);
	
	
	
	

	
	
	
	
	
	
	
	
	
endmodule