基于FPGA的音乐播放器Verilog开发

部分参考代码

(末尾附文件)

module DianZiQin(
	input clk,
	input reset_n,
	
	input play_set,
	input change_set,
	input stop_set,
	
	input [3:0] key_in_y,
	output [3:0] key_out_x,
	
	output alarm,
	
	output [5:0] sm_cs,
	output [7:0] sm_db
);

reg [11:0] clk_100us_cnt;
reg clk_100us_tmp;
reg [3:0] scan_cnt;
reg [3:0] data;

reg [5:0] sm_cs_r;
reg [7:0] sm_db_r;
reg alarm_r;

wire play_set_r;
wire change_set_r;
wire stop_set_r;

reg start_flag;
reg play_flag;

wire speaker;
wire clk_6mhz;
wire clk_4hz;

wire [3:0] high;
wire [3:0] med;
wire [3:0] low; 

wire [3:0] flag_h1_key;
wire [3:0] flag_h2_key;
wire [3:0] flag_h3_key;
wire [3:0] flag_h4_key;

wire audio;
reg [3:0] keynum;

jzjp jzjp(
		  .clk				(clk),              // 开发板上输入时钟: 50Mhz
		  .rst_n				(reset_n),          // 开发板上复位按键
		  .key_in_y			(key_in_y),         // 输入矩阵键盘的列信号(KEY0~KEY3)
		  .key_out_x		(key_out_x),        // 输出矩阵键盘的行信号(KEY4~KEY7) 
		  
		  .flag_h1_key		(flag_h1_key),
		  .flag_h2_key		(flag_h2_key),
		  .flag_h3_key		(flag_h3_key),
		  .flag_h4_key		(flag_h4_key)
);
																
Control Control(
		.clk 					(clk),
		.reset_n 			(reset_n),
	 
		.play_set 			(play_set),
		.change_set			(change_set),
		.stop_set			(stop_set),
		
		.play_set_r			(play_set_r),
		.change_set_r		(change_set_r),
		.stop_set_r			(stop_set_r)
);

FenPin FenPin(
		.clk					(clk),
		.reset_n				(reset_n),
	
		.clk_6mhz			(clk_6mhz),
		.clk_4hz				(clk_4hz)
	);

song song(
		.clk_6mhz			(clk_6mhz),
		.clk_4hz				(clk_4hz),
		.speaker				(speaker),
		.high					(high),
		.med					(med),
		.low					(low),
		.k						(play_flag),
		.start_flag			(start_flag)
);

yy yy( 
		.clk					(clk),
		.audio 				(audio), 
		.clk_6mhz 			(clk_6mhz),
		.clk_4Hz				(clk_4Hz),
		.button				(~start_flag),
		.flag_h1_key		(flag_h1_key),
		.flag_h2_key		(flag_h2_key),
		.flag_h3_key		(flag_h3_key),
		.flag_h4_key		(flag_h4_key)
);

always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		keynum <= 4'd0;
	else begin
		if(start_flag == 1'b0) begin
			if(flag_h1_key[0] == 1'b1) begin
				keynum = 4'd0;
			end

			if(flag_h1_key[1] == 1'b1) begin
				keynum = 4'd1;
			end	
			
			if(flag_h1_key[2] == 1'b1) begin
				keynum = 4'd2;
			end
			
			if(flag_h1_key[3] == 1'b1) begin
				keynum = 4'd3;
			end	
			
			if(flag_h2_key[0] == 1'b1) begin
				keynum = 4'd4;
			end

			if(flag_h2_key[1] == 1'b1) begin
				keynum = 4'd5;
			end	
			
			if(flag_h2_key[2] == 1'b1) begin
				keynum = 4'd6;
			end
			
			if(flag_h2_key[3] == 1'b1) begin
				keynum = 4'd7;
			end	
			
			if(flag_h3_key[0] == 1'b1) begin
				keynum = 4'd8;
			end

			if(flag_h3_key[1] == 1'b1) begin
				keynum = 4'd9;
			end	
			
			if(flag_h3_key[2] == 1'b1) begin
				keynum = 4'd10;
			end
			
			if(flag_h3_key[3] == 1'b1) begin
				keynum = 4'd11;
			end	

			if(flag_h4_key[0] == 1'b1) begin
				keynum = 4'd12;
			end

			if(flag_h4_key[1] == 1'b1) begin
				keynum = 4'd13;
			end	
			
			if(flag_h4_key[2] == 1'b1) begin
				keynum = 4'd14;
			end
			
			if(flag_h4_key[3] == 1'b1) begin
				keynum = 4'd15;
			end
		end
	end
end

always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		alarm_r <= 1'b1;
	else begin
		if(start_flag == 1'b1) begin
			alarm_r <= speaker;
		end
		
		else begin
			alarm_r <= audio;
		end
		
	end
end

always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		start_flag <= 1'b0;
	else begin
		if(play_set_r == 1'b1) begin
			start_flag <= 1'b1;
		end
		
		if(stop_set_r == 1'b1) begin
			start_flag <= 1'b0;
		end
	end
end

always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		play_flag <= 1'b0;
	else begin
		if(start_flag == 1'b1) begin
			if(change_set_r == 1'b1) begin
				play_flag <= ~play_flag;
			end
		end
	end
end

always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		clk_100us_cnt <= 12'h0;
	else begin
		clk_100us_cnt <= clk_100us_cnt + 1'b1;
		if(clk_100us_cnt == 12'h1F4)
			clk_100us_cnt <= 12'h0;
	end
end

always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		clk_100us_tmp <= 1'b0;
	else begin
		if(clk_100us_cnt == 12'h1F4)
			clk_100us_tmp <= 1'b1;
		else
			clk_100us_tmp <= 1'b0;
	end
end

always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		scan_cnt <= 4'd0;
	else begin
		if(clk_100us_tmp == 1) begin
			scan_cnt <= scan_cnt + 1'b1;
			if(scan_cnt == 4'd5)
				scan_cnt <= 4'd0;
		end
	end
end

always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		data <= 4'd11;
	else begin	
		case(scan_cnt)
			4'h0:data <= keynum;	
			4'h1:data <= keynum;	
			4'h2:data <= keynum;	
			4'h3:data <= keynum;
			4'h4:data <= keynum;
			4'h5:data <= keynum;
			default:data <= 4'hB;
		endcase		
	end
end

always@(posedge clk or negedge reset_n) begin
	if(~reset_n)
		sm_cs_r <= 6'b111111;
	else begin
		case(scan_cnt)
			6'h0:sm_cs_r <= 6'b111111;	
			6'h1:sm_cs_r <= 6'b111111;	
			6'h2:sm_cs_r <= 6'b111111;
			6'h3:sm_cs_r <= 6'b111111;
			6'h4:sm_cs_r <= 6'b111111;
			6'h5:sm_cs_r <= 6'b111110;
			default:sm_cs_r <= 6'b111111;
		endcase
	end
end

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链接：https://pan.baidu.com/s/1I0pYd8VDfIE7oBR7cZxxOg
提取码：e6uw

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