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![[architecture]-ARM SMMU学习概念总结一篇就够了_第1张图片](http://img.e-com-net.com/image/info8/d78d5e4d503a43bfa551d2878f68c088.jpg)
目录
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- 前言
- 1、SMMU总结
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- 1.1、SMMU的timeline
- 1.2、SMMU的简介
- 1.3、为什么要使用SMMU?
- 2、MMU IP总结
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- 2.1、CoreLink MMU-700 features
- 2.12、CoreLink MMU-600AE features
- 2.3、CoreLink MMU-600 features
- 2.4、CoreLink MMU-500 Features
- 2.5、CoreLink MMU-401 Features
- 3、总结
- 4、参考
前言
最近朋友圈、微信群(ARM-Trustzone-TEE-AT
)掀起一阵学习SMMU的热潮,作为一名安全领域的渣渣 ,势必要蹭一蹭这个“热点”,也学习一下吧,反正早晚都要学,因为它和安全的关系还是比较大的。学习是一件长期的过程,本文就先简单理一下概念吧。
1、SMMU总结
1.1、SMMU的timeline
![[architecture]-ARM SMMU学习概念总结一篇就够了_第2张图片](http://img.e-com-net.com/image/info8/cf982bd3a5114807b0ff18f7235b43f4.jpg)
1.2、SMMU的简介
SMMU的全称是System Memory Management Units, 它属于Arm的System IP, 主要给其他Master来使用,其连页表格式和Core MMU是一样的,理论上可以让Core的MMU和SMMU使用同一套页表.
那么SMMU都是用在哪些地方呢?*以下展示了一个usecase,来自arm官方博客(February 17, 2014),也是比较早期的一个Sample case
![[architecture]-ARM SMMU学习概念总结一篇就够了_第3张图片](http://img.e-com-net.com/image/info8/2df3e83937174e9a8d18bd0411632d1a.jpg)
1.3、为什么要使用SMMU?
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访问非连续的地址
现在系统中很少再预留连续的memory,如果Master需要很多memory,可以通过SMMU把一些非连续的PA映射到连续的VA,例如给DMA,VPU,DPU使用。
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32位转换成64位
现在很多系统是64位的,但是有些Master还是32位的,只能访问低4GB空间,如果访问更大的地址空间需要软硬件参与交换memory,实现起来比较复杂,也可以通过SMMU来解决,Master发出来的32位的地址,通过SMMU转换成64位,就很容易访问高地址空间。
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限制Master的访问空间
Master理论上可以访问所有的地址空间,可以通过SMMU来对Master的访问进行过滤,只让Master访问受限的区域,那这个区域也可以通过CPU对SMMU建立页表时动态控制。
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用户态驱动
现在我们也看到很多系统把设备驱动做在用户态,调用驱动时不需要在切换到内核态,但是存在一些安全隐患,就是用户态直接控制驱动,有可能访问到内核空间,这种情况下也可以用SMMU来实现限制设备的访问空间
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设备虚拟化
例如设备虚拟化有多种方式,Emulate,Para-virtualized,以及Pass-through,用SMMU可以实现Pass though,这样无论是性能,还是软件的改动都是比较小的。
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一些不支持TrustZone的Master,可以利用SMMU支持Trustzone
2、MMU IP总结
2.1、CoreLink MMU-700 features
- SMMUv3.2 compliant IO-MMU compatible with Arm v8.4 and Arm v9 based CPUs.
- Key Arm architecture features enabled: Secure-EL2, range invalidate, MPAM.
- Support for advanced PCIe and CXL ATS functionality.
- Built to support PCIe Gen5 bandwidth for wide range of I/O applications.
- Introduces AMBA-LTI for translations as a look-aside function.
- Enables the PCIe-PRI feature for on-die accelerators without the need for ATS flow.
2.12、CoreLink MMU-600AE features
- Meets automotive safety requirements for building high-performance ASIL B to ASIL D systems.
- Software compatible with MMU-600 with Arm v8.2 compliant RAS reporting interface.
- Efficient functional logic duplication, ECC and address protection for SRAM.
- AMBA extensions for interface protection.
- Fault management unit to simplify error reporting, testing and integration.
2.3、CoreLink MMU-600 features
- Enhances CoreLink MMU-500 feature set by incorporating SMMUv3.1 specification to support Armv8.2 CPUs.
- Expands the number of contexts supported to millions.
- Implements AMBA-DTI to interface TBU and TCU to improve scalability.
- Multi-level TLB and Walk Cache improves system address translation hit rates.
- Improved write buffer depth and parallel translations.
2.4、CoreLink MMU-500 Features
- Builds on top of MMU-400 features by implementing SMMUv2 architecture adding support for Armv8 CPUs.
- Supports Stage 1, Stage 2, and Stage1 followed by Stage 2 address translation for up to 128 active device contexts.
- Implements a distributed Translation Buffer Unit (TBU) micro-architecture with direct point-to-point connections between each TBU and the centralized Translation Control Unit (TCU) for Page Table Walks (PTWs).
- Supports up to 128 entries per TLB which is further backed by TCU cache up to 2K entries.
2.5、CoreLink MMU-401 Features
- Supports SMMUv1 architecture for Armv7 CPUs and Arm v8 for 64KB page sizes.
- Performs stage2 translation only for hypervisor support.
- Implements a single TBU micro-architecture with connection to a single TCU for page table walks.
3、总结
啥是mmu500,啥是smmu?
mmu500和smmu v3.2的关系,就如同gic500和gicv3的关系。一个是具体的IP,一个是架构。
4、参考
ARM system-memory-management-unit
SMMU跟TrustZone啥关系?