电子科技大学现代电子信息系统综合实验课程EDA频率计
接上一篇博客
https://blog.csdn.net/Jinyindao243052/article/details/107821839
文章目录
- （1）系统功能及指标
- （2）系统设计方案及基本流程
-
- 1.分频器
- 2.控制模块
- 3.计数器
- 4.锁存器
- 5.档位选择模块
- 6.数码管扫描模块
- （3）总体原理框图
- 代码
-
- f_div模块
- control模块
- counter_10模块
- latch模块
- sele模块
- scan_led模块
（1）系统功能及指标
测量范围：20Hz~41MHz(以上)
测量精度：1%以内
（2）系统设计方案及基本流程
1.分频器
对系统时钟(clk)进行分频，分别得到10Hz，100Hz，1kHz的三个不同频率的信号
接口描述：
clk；输入时钟信号
fp_10：10Hz信号
fp_100：100Hz信号
fp_1k：1kHz信号
2.控制模块
功能：控制整个频率计各模块进行时序工作的控制装置，它对输入的标准时钟信号进行变换，产生我们所需要的三个信号闸门信号gate，锁存信号latch以及清零信号reset。
接口描述：
insignal:输入sele模块的输出信号
gate:产生计数器的使能信号，即闸门，频率为insignal的1/10
latch:产生锁存器的时钟信号
reset:产生的计数器的清零信号
control模块其实是一个以insignal为输入时钟的模16计数器，当计数值为0到9时gate为1，其余为0；latch在计数值为11时计数值为1，其余为0；reset在计数值为13时值为1，其余为0。
3.计数器
功能： 6位模10计数器，相当于6个模10计数器级联
接口描述：
ce_signal:输入待测信号作为计数器的时钟
clr:清零信号
en:使能信号
over_l:溢出信号
cnt1~cnt6:计数器计数值，cnt1对应最低位
4.锁存器
功能：对计数器送来的六位计数结果和溢出信号ove_out进行锁存，保证显示数码管的数字不会跳动，方便读取数据。
接口描述：
latch_in：锁存器时钟输入
over_in：溢出信号输入
data_in1~data_in8：分别对应8位数据输入低位到高位
over_out：溢出信号输出
data_out1~data_out6：8位输出数据，分别对应8位输入数据data_in1~data_in6
5.档位选择模块
功能：实现对输入的3个闸门信号的手动选择，将选择的闸门信号由fref输出到下一个模块，同时输出小数点的控制信号dp1。
接口说明：
f1:输入10Hz信号
f10:输入100Hz信号
f100:输入1kHz信号
s:档位选择
s="110"，即key4按下，fref接通f1，dp1<="011"；
s="101"，即key3按下，fref接通f10，dp1<="101";
s="011"，即key2按下，fref接通f100，dp1<="110";
无键按下，默认fref接通低电平’0’，dp默认"110"；
6.数码管扫描模块
功能：对锁存器送来的数据进行动态扫描（即位选）、将六位计数结果分别翻译成七段数码管所能识别的数据（即段选）。
接口描述：
f1k：扫描频率
dp：小数点控制信号
data1~data8：数码管要显示的数据，由低位到高位
dp：小数点控制信号
xs：位选信号，0代表被点亮
sep：段选信号，控制数码管的显示
（3）总体原理框图
代码
f_div模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity f_div is
port (clk : in std_logic;
fp_10,fp_100,fp_1k : out std_logic);
end f_div;
architecture Behavioral of f_div is
signal div_10: std_logic_vector(2 downto 0):="000";
signal div_100: std_logic_vector(2 downto 0):="000";
signal div_1k: std_logic_vector(14 downto 0):="000000000000000";
signal clk_10,clk_100,clk_1k: std_logic;
begin
fen1k: process(clk)
begin
if rising_edge(clk) then
if div_1k=24999 then
div_1k<="000000000000000";
clk_1k<=not clk_1k;
else div_1k<=div_1k+1;
end if;
end if;
end process;
fen100: process(clk_1k)
begin
if rising_edge(clk_1k) then
if div_100=5 then
div_100<="000";
clk_100<=not clk_100;
else div_100<=div_100+1;
end if;
end if;
end process;
fen10: process(clk_100)
begin
if rising_edge(clk_100) then
if div_10=5 then
div_10<="000";
clk_10<=not clk_10;
else div_10<=div_10+1;
end if;
end if;
end process;
fp_10<=clk_10;
fp_100<=clk_100;
fp_1k<=clk_1k;
end Behavioral;
control模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity control is
port( insignal : in STD_LOGIC;
gate : out STD_LOGIC:='0';
latch : out STD_LOGIC:='0';
reset : out STD_LOGIC:='0');
end control;
architecture Behavioral of control is
signal counter_16 : std_logic_vector(3 downto 0):="0000";
Begin
process(insignal)
begin
if rising_edge(insignal) then
counter_16<=counter_16 + 1;
if counter_16 <10 then
gate<='1';
else
gate<='0';
end if;
if counter_16=11 then
latch<='1';
else
latch<='0';
end if;
if counter_16=13 then
reset<='1';
else
reset<='0';
end if;
end if;
end process;
end Behavioral;
counter_10模块
--6个级联的模10计数器
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity counter_10 is
port (ce_signal, clr, en : in std_logic;
over_l : out std_logic;
cn1 : out std_logic_vector (3 downto 0);
cn2 : out std_logic_vector (3 downto 0);
cn3 : out std_logic_vector (3 downto 0);
cn4 : out std_logic_vector (3 downto 0);
cn5 : out std_logic_vector (3 downto 0);
cn6 : out std_logic_vector (3 downto 0);
cn7 : out std_logic_vector (3 downto 0);
cn8 : out std_logic_vector (3 downto 0));
end counter_10;
architecture Behavioral of counter_10 is
signal count1:std_logic_vector(3 downto 0):="0000";
signal count2:std_logic_vector(3 downto 0):="0000";
signal count3:std_logic_vector(3 downto 0):="0000";
signal count4:std_logic_vector(3 downto 0):="0000";
signal count5:std_logic_vector(3 downto 0):="0000";
signal count6:std_logic_vector(3 downto 0):="0000";
signal count7:std_logic_vector(3 downto 0):="0000";
signal count8:std_logic_vector(3 downto 0):="0000";
begin
cn1<=count1;
cn2<=count2;
cn3<=count3;
cn4<=count4;
cn5<=count5;
cn6<=count6;
cn7<=count7;
cn8<=count8;
process(ce_signal,clr,en) is
begin
if clr='1' then
count1<="0000";
count2<="0000";
count3<="0000";
count4<="0000";
count5<="0000";
count6<="0000";
count7<="0000";
count8<="0000";
over_l<='0';
elsif rising_edge(ce_signal) then
if en='1' then
if count1<"1001" then
count1<=count1+1;
else
count1<="0000";
if count2<"1001" then
count2<=count2+1;
else
count2<="0000";
if count3<"1001" then
count3<=count3+1;
else
count3<="0000";
if count4<"1001" then
count4<=count4+1;
else
count4<="0000";
if count5<"1001" then
count5<=count5+1;
else
count5<="0000";
if count6<"1001" then
count6<=count6+1;
else
count6<="0000";
if count7<"1001" then
count7<=count7+1;
else
count7<="0000";
if count8<"1001" then
count8<=count8+1;
else
count8<="0000";over_l<='1';
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
end Behavioral;
latch模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity LATCH is
Port ( latch_in , over_in : in std_logic;
data_in1 : in std_logic_vector (3 downto 0);
data_in2 : in std_logic_vector (3 downto 0);
data_in3 : in std_logic_vector (3 downto 0);
data_in4 : in std_logic_vector (3 downto 0);
data_in5 : in std_logic_vector (3 downto 0);
data_in6 : in std_logic_vector (3 downto 0);
data_in7 : in std_logic_vector (3 downto 0);
data_in8 : in std_logic_vector (3 downto 0);
over_out : out std_logic;
data_out1 : out std_logic_vector (3 downto 0);
data_out2 : out std_logic_vector (3 downto 0);
data_out3 : out std_logic_vector (3 downto 0);
data_out4 : out std_logic_vector (3 downto 0);
data_out5 : out std_logic_vector (3 downto 0);
data_out6 : out std_logic_vector (3 downto 0);
data_out7 : out std_logic_vector (3 downto 0);
data_out8 : out std_logic_vector (3 downto 0));
end LATCH;
architecture Behavioral of LATCH is
begin
process(latch_in)
begin
if rising_edge(latch_in) then
over_out<=not over_in;
data_out1<=data_in1;
data_out2<=data_in2;
data_out3<=data_in3;
data_out4<=data_in4;
data_out5<=data_in5;
data_out6<=data_in6;
data_out7<=data_in7;
data_out8<=data_in8;
end if;
end process;
end Behavioral;
sele模块
--阀门选择
--fref输出1HZ，10HZ，100HZ的信号
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity sele is
port( s: in std_logic_vector(2 downto 0);
f1 ,f10 ,f100 : in std_logic;
fref : out std_logic;
dp1 : out std_logic_vector(2 downto 0));
end sele;
architecture Behavioral of sele is
begin
process(s,f1,f10,f100) --xiaoshudian
begin
case s is
when "110" =>
fref<=f1;
dp1<="011";
when "101" =>
fref<=f10;
dp1<="101";
when "011" =>
fref<=f100;
dp1<="110";
when others =>
fref<='0';
dp1<="110";
end case;
end process;
end Behavioral;
scan_led模块
--扫描模块
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity scan is
Port ( f1k : in STD_LOGIC;
dp2: in std_logic_vector(2 downto 0);
data1 : in STD_LOGIC_VECTOR (3 downto 0);
data2 : in STD_LOGIC_VECTOR (3 downto 0);
data3 : in STD_LOGIC_VECTOR (3 downto 0);
data4 : in STD_LOGIC_VECTOR (3 downto 0);
data5 : in STD_LOGIC_VECTOR (3 downto 0);
data6 : in STD_LOGIC_VECTOR (3 downto 0);
data7 : in STD_LOGIC_VECTOR (3 downto 0);
data8 : in STD_LOGIC_VECTOR (3 downto 0);
xs_out : out STD_LOGIC_VECTOR (7 downto 0);
seg : out STD_LOGIC_VECTOR (6 downto 0);
dp:OUT STD_LOGIC);
end scan;
architecture Behavioral of scan is
signal sel:std_logic_vector (2 downto 0):="000";
signal data:std_logic_vector (3 downto 0);
begin
PROCESS(f1k)
BEGIN
IF RISING_EDGE(f1k) THEN
sel<=sel+1;
END IF;
END PROCESS;
process(f1k,sel,data1,data2,data3,data4,data5,data6)
begin
if rising_edge(f1k) then
case sel is
when"000"=>data<=data1;xs_out<="11111110";
when"001"=>data<=data2;xs_out<="11111101";
when"010"=>data<=data3;xs_out<="11111011";
when"011"=>data<=data4;xs_out<="11110111";
when"100"=>data<=data5;xs_out<="11101111";
when"101"=>data<=data6;xs_out<="11011111";
when"110"=>data<=data7;xs_out<="10111111";
when"111"=>data<=data8;xs_out<="01111111";
when others=>data<="1111";xs_out<="11111111";
end case;
end if;
end process;
dot:
process(sel,dp2)
begin
case sel is
when "100"=>
dp<=dp2(2);
when "011"=>
dp<=dp2(1);
when "010"=>
dp<=dp2(0);
when others=>
dp<='1';
end case;
end process;
process(data)
begin
case data is
when "0000"=>seg<="0000001";
when "0001"=>seg<="1001111";
when "0010"=>seg<="0010010";
when "0011"=>seg<="0000110";
when "0100"=>seg<="1001100";
when "0101"=>seg<="0100100";
when "0110"=>seg<="0100000";
when "0111"=>seg<="0001111";
when "1000"=>seg<="0000000";
when "1001"=>seg<="0000100";
when others=>seg<="1111111";
end case;
end process;
end Behavioral;