HDLbits Count clock 答案

module top_module(
    input clk,
    input reset,
    input ena,
    output reg pm,
    output [7:0] hh,
    output [7:0] mm,
    output [7:0] ss); 
    reg [3:0] ss_ones,ss_tens,mm_ones,mm_tens,hh_ones,hh_tens;
    always@(posedge clk)
        begin
            if(reset)begin
                ss_ones<=4'd0;
                ss_tens<=4'd0;
            end
            else if(ena)begin
                if(ss_ones==4'd9 && ss_tens==4'd5)begin
                    ss_ones<=4'd0;
                    ss_tens<=4'd0;
                end
                else if(ss_ones==4'd9)begin
                    ss_tens<=ss_tens+1'b1;
                    ss_ones<=4'd0;
                   end
                else begin
                    ss_ones<=ss_ones+1'b1;
                end
            end
        end
    always@(posedge clk)
        begin
            if(reset)begin
                mm_ones<=4'd0;
                mm_tens<=4'd0;
            end
            else if(ss_ones==4'd9 && ss_tens==4'd5 && mm_ones==4'd9 && mm_tens==4'd5)begin
                mm_ones<=4'd0;
                mm_tens<=4'd0;
            end
            else if(mm_ones==4'd9 && ss_ones==4'd9 && ss_tens==4'd5)begin
                mm_tens<=mm_tens+1'b1;
                mm_ones<=4'd0;
            end
            else if(ss_tens==4'd5 &&ss_ones==4'd9)begin
                mm_ones<=mm_ones+1'b1;
            end
        end
    always@(posedge clk)
        begin
            if(reset)begin
                hh_ones<=4'd2;
                hh_tens<=4'd1;
            end
            else if(ss_ones==4'd9 && ss_tens==4'd5 && mm_ones==4'd9 && mm_tens==4'd5 && hh_ones==4'd2 && hh_tens==4'd1)begin
                hh_ones<=4'd1;
                hh_tens<=4'd0;
            end
            else if(hh_ones==4'd9 && ss_ones==4'd9 && ss_tens==4'd5 && mm_ones==4'd9 && mm_tens==4'd5)begin
                hh_tens<=hh_tens+1'b1;
                hh_ones<=4'd0;
            end
            else if(ss_tens==4'd5 &&ss_ones==4'd9 && mm_tens==4'd5 && mm_ones==4'd9)begin
                hh_ones<=hh_ones+1'b1;
            end
        end
            
            assign ss={ss_tens,ss_ones};
            assign mm={mm_tens,mm_ones};
            assign hh={hh_tens,hh_ones};
                
    always@(posedge clk)
        begin
            if(reset)begin
                pm<=0;
            end
            else if(ss_tens==4'd5 &&ss_ones==4'd9 && mm_tens==4'd5 && mm_ones==4'd9 && hh_tens==4'd1 && hh_ones==4'd1)begin
                pm<=~pm;
            end
        end
endmodule

Create a set of counters suitable for use as a 12-hour clock (with am/pm indicator). Your counters are clocked by a fast-running clk, with a pulse on ena whenever your clock should increment (i.e., once per second).

reset resets the clock to 12:00 AM. pm is 0 for AM and 1 for PM. hh, mm, and ss are two BCD (Binary-Coded Decimal) digits each for hours (01-12), minutes (00-59), and seconds (00-59). Reset has higher priority than enable, and can occur even when not enabled.

The following timing diagram shows the rollover behaviour from 11:59:59 AM to 12:00:00 PM and the synchronous reset and enable behaviour.