[HDLBits] Fsm3s

See also: State transition logic for this FSM

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include a synchronous reset that resets the FSM to state A. (This is the same problem as Fsm3 but with a synchronous reset.)

State	Next state		Output
	in=0	in=1
A	A	B	0
B	C	B	0
C	A	D	0
D	C	B	1

module top_module(
    input clk,
    input in,
    input reset,
    output out); //
	parameter a=0,b=1,c=2,d=3;	
    reg [1:0]state,next;
    always@(*) begin
        case(state)
            a:next<=in?b:a;
            b:next<=in?b:c;
            c:next<=in?d:a;
            d:next<=in?b:c;
        endcase
    end

    always@(posedge clk) begin
        if(reset)
            state<=a;
        else
            state<=next;
    end
    // Output logic
	assign out=state==d?1:0;
endmodule