UVM sequence机制（4）（response 特性）

这篇我们介绍一下sequence 机制的response 属性。

/sequence1

class sequence1 extends uvm_sequence;
............................
............................

virtual task body();

     item1    req1;
     item1    rsp1;
     repeat(10) begin
	       req=new("req1");
		   start_item(req1);
		   ...............
		   finish_item(req1)
		   get_response(rsp);
	       .........................
	       .........................
	       .........................
	 end

endtask


endclass
/sequence1
///driver
class my_driver extends uvm_driver #(item1);
      .......................
      .......................
      .......................
      virtual task run_phase(uvm-phase phase)；
                         ......................
                         ......................
                         seq-item_port.get_next_item(req);
                         ...................................................
                         ......