HDLBits-Fsm3

See also: State transition logic for this FSM

The following is the state transition table for a Moore state machine with one input, one output, and four states. Implement this state machine. Include an asynchronous reset that resets the FSM to state A.

State	Next state		Output
	in=0	in=1
A	A	B	0
B	C	B	0
C	A	D	0
D	C	B	1

Module Declaration

module top_module(
    input clk,
    input in,
    input areset,
    output out); 

在编写状态机装换代码时，可以发现采用独热编码代码比较简单。

以下为代码：

module top_module(
    input clk,
    input in,
    input areset,
    output out); //
    reg[3:0] state;
    // A 0001  B 0010  C 0100 D 1000
    parameter A = 0,
              B = 1,
              C = 2,
              D = 3;
    // State transition logic
   
    // State flip-flops with asynchronous reset //异步reset
    always @(posedge clk or posedge areset) begin
        if(areset)begin 
            state <= 4'b0001;
        end
        else
        begin 
              state[A] <= state[A]&(~in) | state[C]&(~in);
              state[B] <= state[A]&in | state[B]&in | state[D]∈
              state[C] <= state[B]&(~in) | state[D]&(~in);
              state[D] <= state[C]∈
        end
    end
    // Output logic
    assign out = state[D];
endmodule

由于采用异步置位areset，因此要用always @(posedge clk or posedge areset)

不能将置位和状态转换写在两个模块中，否则会造成多驱动错误。