HDLbits练习:Lemmings2

In addition to walking left and right, Lemmings will fall (and presumably go "aaah!") if the ground disappears underneath them.

In addition to walking left and right and changing direction when bumped, when ground=0, the Lemming will fall and say "aaah!". When the ground reappears (ground=1), the Lemming will resume walking in the same direction as before the fall. Being bumped while falling does not affect the walking direction, and being bumped in the same cycle as ground disappears (but not yet falling), or when the ground reappears while still falling, also does not affect the walking direction.

Build a finite state machine that models this behaviour.

在前一道题的基础上增加了一个掉落（DROP）的状态。

 

 时序图如下题目给出的参考状态转移图由4个状态组成，但是用三个状态也可以完成，增加一个变量记忆掉落之前的状态就行。

 

module top_module(
    input clk,
    input areset,    // Freshly brainwashed Lemmings walk left.
    input bump_left,
    input bump_right,
    input ground,
    output walk_left,
    output walk_right,
    output aaah ); 
    parameter LEFT=0,  RIGHT=1, DROP=2;//增加一个掉落的状态
    reg[3:0] state, next_state, memory;//创建memory用于存储掉落前的状态

    always @(*) begin
        case(state)
            LEFT:begin
                    if(!ground)begin
                        next_state=DROP;
                    end
                    else if (bump_left)begin
                        next_state=RIGHT;
                    end
                    else begin
                        next_state=LEFT;
                    end
                    memory=LEFT;
            end
           
            RIGHT:begin
                      if(!ground)begin
                      	next_state=DROP;
                      end
                      else if(bump_right)begin
                      	next_state=LEFT;
                      end
                      else begin
                      	next_state=RIGHT;
                      end
                      memory=RIGHT;
           end
            DROP:begin
                     if (!ground)
                     	next_state=DROP;
                     else 
                     	next_state=memory;
            end      
        endcase
    end

    always @(posedge clk, posedge areset) begin
        // State flip-flops with asynchronous reset
        if(areset)
            state<=LEFT;
        else
            state<=next_state;
    end

    // Output logic
    assign walk_left = ((state == LEFT));
    assign walk_right = ((state == RIGHT));
    assign aaah =((state == DROP));

endmodule